IBM, the EV Group, NEXX Systems,
Surface Technology Systems, SUSS
Microtech, and Tezzaron are investigating
3D TSV interconnects. Other interested
organizations include the Fraunhofer
Institute of Technology, Georgia Institute
of Technology, IMEC, Taiwan Semiconductor
Manufacturing Company (TSMC),
and Tohoku University.
TSV manufacturing proposals include
chip-to-chip, chip-to-wafer, wafer-towafer,
TSV first, TSV last, and self-assembly
production methods. None has seen
wide-scale adoption, nor have the many
competing TSV materials like copper-tocopper,
copper-to-gold, and solder.
Working with Cubic Wafer Inc., Aviza
Technology is proposing a die-to-wafer
stacking technology that will produce
TSVs with 15-µm diameters and 100-µm
depths within a CMOS IC having 90-nm
line features. The vias are formed by etching
a 9-µm thick dielectric that consists of
40 layers. A deep silicon etch system next
forms the TSVs. Ionized physical-vapor
deposition (PVD) is then used to form a
barrier and seed metal.
According to Aviza, this ionized PVD
is better than a conventional PVD process
because it allows TSV scallop depths of 0.4
µm and mask undercuts of 0.5 µm with
2.5 µm of tetraethyl orthosilicate (TEOS)
material. Void-free copper plating completes
the TSV. Aviza already has a Versalis
fxP cluster system for 3D stacking that
handles 200- and 300-mm wafers.
RF CHALLENGES
One challenge for SiP development is in
the wireless RF arena, with the omnipresent
mobile phone. Existing approaches
that use ceramic packages or silicon passive
components have proven costly and can’t
always meet the high levels of integration
often desired. An improvement for RF
SiP substrates has come from a patented
thin-film multilayer organic process developed
by Rogers Corp. working with Jacket
Micro Devices (Fig. 5).
The approach combines advanced RF
circuit materials based on liquid-crystalline
polymers (LCPs) and ceramic-filled
polytetra-fluorethylene (PTFE) composites,
coupled with novel processing and circuit
topologies. To maximize integration
levels, the materials feature low loss at high
frequencies, a stable dielectric constant,
good laser micro-via capability, low moisture
absorption, and good thermal stability.
The end result is high performance and
high reliability.
At the chip-scale level, Avago Technologies
announced a breakthrough in packaging
that brings wireless chip micro-miniaturization
and high performance to new
levels. The company claims its WaferCap
is the industry’s first semiconductor-based
gallium-arsenide (GaAs) CSP FET (Fig.
6). It provides the lid while the basic wafer
incorporates the active device.
The pseudomorphic-high-electron-mobility-
transistor (pHEMT) is a lownoise
device with a frequency range of 500
MHz to 12.5 GHz, with the potential to
reach 100-GHz operation. The surfacemount
package has the same dimensions as
an 0402-size component, measuring 1 by
0.5 by 0.25 mm, and can reduce the space it
requires on a PCB by more than 50%.