Shorter development times and and cost-effective miniaturization make for an unbeatable combination. Those just happen to be the attributes of the quickly rising system-in-a-package (SiP) technology. In a straightforward manner, SiPs can also integrate a number of heterogeneous technologies—for example, a variety of silicon ICs and discrete components—in a minimal footprint.
Present SiPs can incorporate microprocessors, memories (like EPROMs and DRAMs), FPGAs, resistors, capacitors, and inductors in a package that holds up to four or five die. Several companies leading the pack in developing SiP solutions aren't just coming up with their own approaches, though. They're also working with leading IC chip manufacturers on novel SiP solutions (see "A Rosy Outlook For SiP Technology," p. 50).
To a large extent, SiP technology has stepped in to fill the void left by system-on-a-chip (SoC) technology's higher development and non-return engineering (NRE) costs and longer time-to-market. New SoCs require significant investments in time and money, something that many products (particularly those on the consumer end) can't afford.
For instance, some SoCs can take 18 months to reach the market, while SiPs can cut that time by 50% or more. With their vertical integration, SiPs can shorten interconnect distances as well. This reduces signal delay times, noise, and capacitance effects, allowing higher signal speeds. Power dissipation is lower too.
In some cases, SiPs serve as an interim step for further SoC development that will eventually merge everything onto one silicon chip. This is particularly true in Bluetooth devices, cell phones, automotive electronics, imaging and display products, digital cameras, and power supplies.
SiPs have adapted well to the packaging needs of these applications, often slashing real-estate area by up to 80% and weights by 90% compared to conventional IC packages. One key reason behind those numbers is the use of surface-mount technology (SMT). SiP technology blends the SMT of electronic manufacturing services (EMS) with those of semiconductor assembly services (SAS).
SiPs started out by stacking memory and logic chips together for many consumer applications. In fact, Intel recently developed a folded-stack chip-scale package (CSP) SiP with logic and memory (Fig. 1). In 1998, Sharp Corp. introduced the first stacked chip-scale package consisting of bare die flash memory and SRAMs for use in cellular phones.
Many other companies followed suit. Valtronic SA uses the folded concept to combine logic, memory, and passive components into a single SiP for use in hearing aids and heart pacemakers (Fig. 2). Now, companies are trying to add microprocessors, power devices, passives, and other functional components.
The folded-stack CSP in use by many companies uses Tessera's patented 3D mZ fold-over ball stack concept, which the company pioneered in the mid-1990s, for high-reliability applications. The concept allows up to eight DRAM, SRAM, or flash memory chips to be stacked into a multichip assembly. It uses a flat, flexible polyimide tape that's attached to a chip die and then folded over for interconnecting the next stacked die on top.
The convergence of video, audio, and data is a large driving force for using the SiP concept. "The integration of data, voice, and video in smart phones and PDAs requires higher performance, longer battery life, and increasing memory density in a sleek package," says Hyung Lae Ruh, executive vice president for Samsung's R&D Center. "Our SiP solution offers the first combination of an application processor with NAND flash memory."
SiP solutions come in various shapes: stacked-chip structures that target small form-factor needs; side-by-side solutions for I/O terminal functions; chip-on-chip (CoC) form factors for high-frequency and low-power operation; multichip modules (MCMs) for higher packing densities; and chip-on-board (CoB) structures for large memory devices. In many of these form factors, chips and other components are integrated vertically within a small footprint. Often, SiP is referred to as 3D packaging.
In fact, third-dimensional (vertical or z axis) manufacture of IC chips is an ongoing R&D effort with its own successes. This shouldn't be confused with 3D packages that put different functions (memory, logic, CPUs) on different chips and then stack them together in one package.
Instead, SiP packaging takes advantage of much shorter chip interconnect lead lengths. This is the same goal for 3D silicon ICs, because increasingly complex ICs have become more difficult to connect to one another.
A key development in SiP technology is the introduction of SiliconPipe's Off-The-Top (OTT) technology. The concept enables high-speed (more than 20 Gbits/s over a distance of 3 in.) signals to transmit off the top of one package on a uniform impedance-matched transmission line to the top of another package. Such a concept could ultimately push designers toward an SiP approach instead of an SoC design (Fig. 3).
According to Mark Bird, senior director of technical marketing for Amkor, and Joseph Adam, vice president for strategic marketing at Skyworks Solutions Inc., the most common types of SiP packages are stacked-die packages, stacked packages (package atop a package), and modules (Fig. 4). Laminate-substrate SiPs are the most dominant, with ceramic, lead-frame, and tape substrate use on the rise.
Amkor employs the SiP concept for digital cameras, where it uses laminate substrates that are built in matrix strips. A flexible circuit contains components and a connector as well as a pc-board-mounted image sensor. On top of all this sits a module that houses the camera's barrel, lens, infrared glass, mount, and adhesives (Fig. 5). According to Amkor, its approach follows standard handling and permits the use of standard equipment, thus lowering costs.