Untitled DocumentDynamic Power Management of Microprocessors
Heatsinks and fans can only go so far to cool microprocessors. Also, sleep and suspend modes that reduce power consumption can disable system operation. There is a need for a power-performance tradeoff because clock rates are moving higher and there are more transistors per package, which increases operating current and power dissipation.
Although performance has increased, power efficiency is still critical in embedded computer systems because lower power cuts operating costs, reduces the necessary fan noise, and lowers cooling requirements. It is also important in battery-based systems where lower power consumption extends useful battery life.
The goal of lowering power has led to new circuit techniques, called dynamic power management (DPM), that reduce a microprocessor's average power dissipation by dynamically reconfiguring a system to lower power consumption during low-workload periods. The clue to reducing power dissipation rests on the system power consumption equation of CMOS ICs:

where:
P = system power consumption
C = total capacitance of all circuits that need to be charged during signal transitions
V = applied voltage
F = frequency
Therefore, C is a constant. Reducing the operating voltage or frequency, or both, will lower overall system power consumption. However, reducing the supply voltage may also reduce the operating frequency, so it's not exactly a linear relationship.
In principle, DPM identifies low processing-requirement periods and reduces operating voltage (voltage scaling) and/or frequency (frequency scaling) to reduce operating power consumption. This technique is called dynamic voltage and frequency scaling (DVFS). During these low power-requirement periods, idle circuits can be turned off to save even more power.
Proposed DPM solutions can be categorized as either predictive or stochastic. Predictive schemes attempt to predict a device's usage behavior in the future, based on past experience. Stochastic techniques make probabilistic assumptions based on usage pattern observations.
To be effective, DPM must account for the time it takes to change a power-supply voltage. Plus, the processor must be able to operate reliably when its supply voltage or clock rate changes.
The introduction of multicore processors will require a more sophisticated approach to reduce power consumption. A technique proposed by James Donald and Margaret Martonosi of Princeton University (2006 International Symposium on Computer Architecture, ISCA06) employs "a multi-loop mechanism that allows the operating system and the processor hardware to collaborate on a robust, stable, and effective thermal management policy." The researchers know of no other architecture work exploiting multi-loop control.