In his comments at the 3D Systems Integration and Packaging Conference last month in Burlingame, Calif., Ho-Ming Tong, chief R&D officer and general manager of group R&D at ASE Group, quoted Victor Hugo, saying “You can resist an invading army, but you cannot resist an idea whose time has come.” Thus describes the general industry consensus that as scaling reaches its outer limits, 3D technologies will be set to take up the gauntlet of furthering Moore’s Law.
Frost & Sullivan included 3D integration in its latest Global Top 10 Hot Technologies to Invest. According to Kasthuri Jagadeesan, senior research analyst of technical insights at Frost & Sullivan, target market segments for 3D integration include CMOS image sensors (CIS), memory, processors, and FPGAs.
Further, Jagadeesan notes that with companies such as Intel, NEC, NXP Semiconductors, Tessera, Samsung, STMicroelectronics, and Amkor Technologies involved in driving the efforts in the 3D space, strategies such as application-centric collaborations exploring new applications could accelerate the commercialization prospects of 3D IC technology (Fig. 1).
Technologies that exploit the Z-direction have been around for quite some time, such as package-on-package, chip stacks with wire bond interconnects, embedded die, and fan-out and fan-in wafer-level packaging (WLP). Yet the challenge is finding the right method to achieve functional density at desired cost.
“It’s not going to be wire bond. It’s going to be TSV,” predicts Bill Bottoms, chairman of NanoNexus and iNemi. Through-silicon via (TSV) provides a shorter method of interconnect that allows for faster speed and lower power consumption.
Research by Yole Développment shows that despite a worldwide economic recession, the R&D activity linked to 3D companies has reached “unprecedented levels.” Jeff Perkins, general manager of Yole, predicts that 3D TSV technologies will be one of an assortment of offerings by 2015.
Perkins also describes a “3D packaging toolbox” that by 2013 will consist of 62% 3D TSV stacks, 18% 3D interposer modules, and 18% 3D WLP devices. He advises companies to pick their opportunities by looking for the ones that are trending toward 3D.
With regards to 3D TSV applications specifically, Jan Vardaman, president of TechSearch International, predicts timing for expected volume production by applications as:
- CIS: volume production today
- DRAM server applications: 2011-2012
- DRAM with processor for wireless applications: 2012 and later
- FPGA possible introduction: 2012-2013
- Microprocessors with memory: possibly by 2014
“Our definition of volume production is being able to take a cell phone, laptop, what have you, tear it apart, and voila—find a TSV device inside,” Vardaman says. “It’s not a matter of doing the technology. It’s a matter of when it makes sense of adopting it in products.”
TURNING TO TSVS
For a long time, TSVs were considered too costly an option as a method of interconnect. Now we’re seeing them discussed as a cost-saving alternative. So what changed? Two things: the point of reference and the cost of manufacturing TSVs themselves.
The point of reference for cost comparison is whether you’re comparing the cost to wire bond or to the cost of scaling. TSV interconnects offer performance advantages in both realms. But while designers would switch from wire bond to TSV to improve performance, not save costs, TSV solves the density, performance, and cost issues when it comes to device scaling.