Imagine that your flight from San Francisco to New York takes off in three hours. During the long flight, you’d love to watch the new season of your favorite show or a movie that a friend recommended, but you might think there’s not enough time to complete the download before you have to leave.
Thankfully, technological innovations are happening at a pace that enables users to get the content they want a lot faster. One such evolution is that of the most universal and ubiquitous interface—the Universal Serial Bus (USB). The new USB 3.0 specification supporting SuperSpeed rates is here and promises to be the panacea to such situations.
Thanks to the Internet and the communications revolution, an enormous amount of content is being generated, processed, and consumed at a staggering rate. In parallel, mass storage technologies are seeing significant innovation. Storage is becoming inexpensive and densities are increasing, driving content sharing. Users no longer worry about conserving hard-drive space.
Yet so strong is the need for a faster interconnect technology that several technology leaders have come together to solve this problem in an elegant and seamless manner. The USB Implementers Forum recognized this urgent need for a next-generation interconnect technology and ratified USB 3.0 in November 2008.
HISTORY OF USB
USB 3.0 is the next stage of USB technology. Its primary goal is to provide the same ease of use, flexibility, and hot-plug functionality but at a much higher data rate. Another major goal of USB 3.0 is power management. This is very important for “Sync & Go” applications that need to trade off features for battery life.
Chipsets are expected to begin shipping in 2010, with broad deployment in 2011. A variety of USB 3.0-based products including PC motherboards, hard drives, PCI Express (PCIe) add-on cards, and cameras were showcased in industry events in 2009, and more products are expected to be released in early 2010.
USB 3.0 heralds an all-new wave of application usage models and is expected to deliver actual throughput greater than 3 Gbits/s (raw signaling speed of 5 Gbits/s), which is more than 10 times higher than that of Hi-Speed USB. Initially, USB 3.0 will target the PC market and devices requiring high rates and volumes of data transfer, such as external storage, consumer electronics, and communications products with increasing amounts of storage.
FROM HI-SPEED TO SUPERSPEED
The USB 3.0 interface consists of a physical SuperSpeed bus in addition to the physical USB 2.0 bus. The USB 3.0 standard defines a dual simplex signaling mechanism at a rate of 5 Gbits/s. This enables simultaneous transfer of data to and from the device as opposed to the single duplex unidirectional USB 2.0 bus.
The architecture is designed to be electrically and mechanically backward compatible with USB 2.0, so a USB 3.0 host would communicate with a device at the fastest signaling rate supported by the device. Conversely, a USB 3.0-compliant device would seamlessly function at the USB 2.0 signaling rate when plugged into a USB 2.0 host.
In addition to a signaling rate that’s 10 times faster than USB 2.0, USB 3.0 supports a significantly more efficient transfer model, such as asynchronous notifications replacing the polling model of USB 2.0. As an example, when the USB 3.0 host initiates a transaction, the device may respond with Not Ready (NRDY) if data or buffer space is not available. Later, when the device can honor the request, it will report an Endpoint Ready (ERDY) status to the host.
A USB 2.0 host broadcasts packets to all enabled downstream devices, forcing all devices to decode the address received with every packet. In contrast, a USB 3.0 host unicasts packets only to the target device by embedding routing information in transmitted packets, which an intermediating hub decodes.
This model of unicast packets allows inactive devices to remain in a low-power state, and it’s one of the several power-saving techniques implemented by USB 3.0. The USB 3.0 specification (see the table) also lets devices draw up to 900 mA when attached to a host, which is significantly higher than the 500-mA limit set by USB 2.0.
USB 3.0 ARCHITECTURE
The layered PCIe architecture and the OSI model inspired the USB 3.0 architecture (Fig. 1). It has a physical layer (PHY), link layer, and protocol layer. The PHY includes the connection between a host and a device or a hub and a device. Similar to the PCIe PHY, the USB 3.0 PHY includes 8b/10b encoding/decoding, data scrambling and descrambling, and serializing and deserializing functions.
The link layer maintains link connectivity and ensures data integrity between link partners by implementing error detection. Packets are created in the link layer, and link commands are issued. The protocol layer manages end-to-end data flow between a device and a host.
Like USB 2.0, the SuperSpeed bus carries data, address, status, and control information. Four packet types are defined. Two of them, the Transaction Packet (TP) and Data Packet (DP), remain the same as in USB 2.0. Two additional packet types, Isochronous Timestamp Packet (ITP) and Link Management Packet (LMP), are newly introduced by USB 3.0.
USB 3.0 POWER MANAGEMENT
USB 3.0 provides enhanced power-management capabilities to address the needs of battery-powered portable applications. Two “Idle” modes (denoted as U1 and U2) are defined in addition to the “Suspend” mode (denoted as U3) of the USB 2.0 standard.
The U2 state provides higher power savings than U1 by allowing more analog circuitry (such as clock generation circuits) to be quiesced. This results in a longer transition time from U2 to active state. The Suspend state (U3) consumes the least power and again requires a longer time to wake up the system.