A fourth generation IGBT co-packaged with an ultrafast, soft-recovery, anti-parallel diode is optimized for minimum saturation voltage and low operating frequencies (CE(on) is 1.4 V at 10 A. Tailored for extremely low forward-voltage drop and reverse leakage current, the co-packaged diodes across the low-side IGBTs are optimized to minimize losses during freewheeling and reverse recovery. The switching techniques in this design offer a number of advantages:
• Achieving high efficiency by permitting high-side and lowside IGBTs to be optimized separately.
• No freewheeling on the highside, co-packaged, soft-recovery diodes, eliminating unnecessary switching losses.
• Switching low-side IGBTs at a low frequency of 60 Hz, as conduction loss dominates these IGBTs.
• No cross conduction, since switching is done on a diagonal device pair at any time (Q1 and Q4 or Q2 and Q3). Hence, there’s no possibility of bus shoot-through, because the IGBTs on the same leg of the bridge never switch in a complementary fashion.
• Co-packaged, ultrafast, soft-recovery diodes across the low-side IGBTs can be optimized to minimize losses during freewheeling and reverse recovery.
FUNCTIONS AND PERFORMANCE
In the system-level power inverter circuit, each leg of the H-bridge is driven using a high-voltage, highspeed, gate-driver IC with independent low- and highside referenced output channels (Fig. 3). The driver IRS2106SPBF’s floating channel permits bootstrap power- supply operation for the high-side power transistors.
As a result, it eliminates the requirement for an isolated power supply for the high-side drive. This translates into improved efficiency for the inverter and parts count reduction for the overall system. The bootstrap capacitors for these drivers get refreshed every switching cycle when current freewheels on the low-side IGBT’s co-package diodes.
Because high-side Q1 and Q2 co-packaged diodes aren’t subjected to the freewheeling current and the low-side Q3 and Q4 diodes exhibit mostly conduction loss and very little switching loss, overall system losses are minimized and system efficiency is maximized. The cross-conduction possibility also is eliminated since the switching is implemented on a diagonal device pair only at any time (Q1 and Q4 or Q2 and Q3).
In addition, each of the output driver ICs features a high-pulsecurrent buffer stage that’s designed to minimize driver cross-conduction. Furthermore, because the system operates from a single dc bus supply, it eliminates the need for a negative dc bus. For the overall system, all of these factors translate into higher efficiency and lower parts count. Fewer components also mean less space and a smaller bill of materials.
In this inverter design, a +20-V supply is first applied to power the microprocessor and the housekeeping circuits. For the source code that’s implemented, the 8-bit PIC18F1320 microcontroller used in this inverter scheme generates the signals for the IGBT drivers that eventually generate the signals to drive the IGBTs accordingly.
Speaking of drivers, the low-side and highside IGBT drivers used in this design are fabricated in a proprietary, advanced highvoltage IC process (G5 HVIC) and latch immune CMOS technologies to operate to 600 V. They also incorporate high-voltage level-shifting and termination techniques that enable the drivers to generate the appropriate gate-drive signals from low-voltage input coming from the microcontroller. The logic input is compatible with standard CMOS or low-power Schottky transistor-transistor logic (LSTTL) output, down to 3.3- V logic.
Ultrafast diodes D1 and D2 provide the path to charge capacitors C2 and C3 and ensure that the high-side drivers are correctly powered. During the positive output half-cycle, the high-side IGBT Q1 is sine PWM modulated, while the low-side Q4 is kept on (Fig. 4). Similarly, during the negative output half-cycle, the high-side Q2 is sine PWM modulated while the low-side Q3 is kept on. This switching technique produces a 60-Hz ac sine wave across output capacitor C4, following the LC filter.
With the inverter designed for an output of 500 W, measured ac output power was 480.1 W with a power loss of 14.4 W. The ac output voltage at 60 Hz was 117.8 V with 4.074-A output current. Figure 5 illustrates the 60-Hz waveform for this 500-W output.
The setup’s measured efficiency was 97.09%. Using a similar setup, the inverter was next tailored for 200-W output, and the conversion efficiency was measured again. The ac power at the load was 214 W with a power loss of 6.0 W. The 60-Hz output voltage was 124.6 V at 1.721-A output current. Conversion efficiency measured at this power rating was 97.28%. A similar efficiency performance was observed even at the lower end of the output power, which is 100 W.
Figure 6 shows the inverter power loss measured for output power levels going from about 100 to 500 W. When inverter efficiency was measured across a similar output power range for the same dc input, high output efficiency of greater than 97% was maintained across a broad range of output power, even though the power loss increases as the output power goes higher (Fig. 7).
In conclusion, with the right combination of drivers and lowand high-side IGBTs, this solar-power inverter design delivers a consistently high power-conversion efficiency performance from about 100-W output to nearly 500 W. Because the efficiency is high, the low power dissipation didn’t present any thermal-management challenges. Consequently, the demo board on which the drivers and high voltage IGBTs were mounted operated without a fan up to 500 W.2
REFERENCES
1. Chou, Wibawa, “Choose Your IGBTs Correctly for Solar Inverter Applications,” Power Electronics Technology, August 2008, p. 20.
2. “DC to AC Inverter IGBT Demo Board” Wibawa T. Chou, applications engineer, holds a BSEE and MSEE from Ohio State university, Columbus, Ohio.
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