MAKING IT EASIER TO DEBUG
Debugging on an 8-bit microcontroller without ICE (in-circuit emulation) hardware can be an exercise in patience. Developers using 32-bit processors are used to much more.
To ameliorate that situation, many of the Cortex M3's features use single-wire interfaces, which helps reduce pin count. The processor may also include Arm's standard embedded trace module (ETM) feature. ETM output is supported by a number of hardware trace systems.
The debug access port (DAP) provides access to all memory and registers in the system. Also, all interrupt vector information is available. The single-wire viewer (SWV) supplies real-time feedback without having to stop or slow down the processor. It can be used to provide hardware profiling without the need for program instrumentation.
The Flash Patch feature offers a way to hook into program code without modifying flash memory. In this case, flash memory is mapped to data RAM. This can be handy for debugging, as well as for making dynamic system changes.
Arm-class breakpoint and watchpoint services come with the Data Watchpoint and Trigger Unit (DWT). This includes eight hardware breakpoints courtesy of the Flash Patch feature and two hardware watchpoints. The Cortex M3 supports stepping modes with or without interrupts.
Cortex M3 power-management support includes three sleep modes. Sleep Now waits for interrupts in power-down mode. Sleep On Exit puts the system in power-down mode when an interrupt-services routine ends. The system is even smart enough not to restore a task's state, because only an interrupt can exit this mode. Finally, the Deep Sleep mode shuts down the phase-locked loop (PLL). Sleep modes can also control clocks and peripheral power outside the core.
Arm has worked with third-party vendors to deliver operating systems, compilers, and support software such as system libraries that only utilize Thumb and Thumb/Thumb 2 instructions. Bit manipulation instructions will improve RTOS performance. Developers may need to recompile their application and libraries when targeting the Cortex M3. Third-party hardware debug vendors have also worked with Arm to provide access to the new debugging support.
The Cortex M3 will be licensed in a fashion similar to Arm's existing portfolio of intellectual property. Expect the architecture to be implemented by third-party hardware vendors that currently have standard, off-the-shelf Arm-based processors as well as custom designs. Many of the standard components will benefit from the Cortex M3's new architecture since they are targeted at compact, low-power applications that are readily addressed by the Thumb and Thumb 2 instruction sets.
The Cortex M3 is a major change of direction for Arm. Ultimately, the design opens up 32-bit computing on a standard platform to the world of 8- and 16-bit developers.
Arm Ltd.
www.arm.com