EMBEDDING 64 BITS
MIPS Technologies recognized early on that the desktop and server market was getting a bit crowded, and the embedded environment was growing tremendously. It's now one of the dominant 32- and 64-bit vendors in this arena. But don't look for MIPS chips from MIPS Technologies because it licenses designs to vendors like Broadcom.
Single-processor-core MIPS chips have been the norm, but its compact design and rising transistor counts have led to quad processor chips. MIPS architects have kept a number of tenets in mind, such as "don't add instructions to an architecture that would impede implementation." A streamlined design leads to higher performance with minimal hardware.
Because of the IP-oriented nature of MIPS Technologies, the incarnation of MIPS processors is quite varied. Low-end 64-bit processors may incorporate only a level 1 cache, while others may implement a four-way superscalar core. Minimizing cache complexity can improve determinism that's necessary in many embedded environments. In many instances, custom instructions are added to the standard MIPS instruction set. The 64-bit architecture supports compact 32-bit instructions, as well as 64-bit instructions and even DSP-style instructions.
MIPS' multithreading support includes two key features: virtual processor emulation (VPE) and fine-grain thread support. These enhancements to the architecture raise the number of simultaneous threads that a particular implementation can handle.
The embedded arena has different demands compared to desktop and servers. Low interrupt latency, fast task switching, and bit-manipulation instructions are key to the success to the MIPS64 architecture.
64 BITS FOR THE ENTERPRISE
Look under the hood of large enterprise clusters and the engine you'll find is Sun's 64-bit UltraSparc processor. One of the first successful RISC architectures, the UltraSparc has been available in a variety of incarnations. Occasionally, it has found a home in high-end embedded applications, but its real calling is high-performance workstations and servers.
The architecture uses a register window design instead of a memory-based stack. This proven technology is similar to the one adopted in Intel's EPIC architecture. The UltraSparc has included a number of features now appearing in other 64-bit designs, such as an integrated memory controller. Its 4-Mbyte maximum page size helps keep large memory applications (e.g., database servers) humming. The UltraSparc III and IV are designed to work well in multiprocessor systems from dual-processor systems through systems with hundreds of processors.
The newest UltraSparc design employs a dual-processor core design. Each can execute four instructions using a superscalar design. Niagra, the next-generation design, promises to incorporate eight processor cores on a single chip, with each core handling up to four threads at a time for a whopping total of 32 threads per chip.
While good compilers are key to the success of many 64-bit processors, the Solaris operating system has been key to the success of the UltraSparc. Managing large multiprocessor systems isn't simply a matter of increasing the size of a control array. Of course, keeping Solaris on top means that the UltraSparc architecture must keep delivering the underlying hardware performance.