Toshiba America Electronic Components (TAEC) has a new 8-bit microcontroller core with performance comparable to that of 16-bit MCUs. The TLCS-870/C1 core can process one instruction in a single clock cycle, enabling faster processing at lower frequencies, reduced noise, and lower power consumption compared with the company’s previous 8-bit cores.
The core has a large-capacity address space that’s expandable to 128 kbytes. It’s well suited for a wide range of jobs, from small-scale applications like portable devices to large-scale applications requiring large-capacity ROM, such as air conditioners, washing machines, and other white goods.
The expanded address space was attained with a memory-management method that manages code and data in separate areas. Up to 128 kbytes of address space can be implemented in an 8-bit MCU without any adverse consequences. Such consequences could include increased footprint due to address-bus expansion or degraded processing speed, which is common with the alternative memory-bank method.
The new core family helps reduce system cost by integrating must-have features such as a voltage-detection circuit, a power-on reset circuit, and an on-chip debug circuit. The TLCS-870/C1 core is binary compatible with previous Toshiba 8-bit MCUs, so existing software resources can be used.
TAEC plans to introduce its first new products based on the new core in the fourth quarter of 2006.
Toshiba America Electronic Components
http://chips.toshiba.com
Toshiba America Electronic Components (TAEC) has a new 8-bit microcontroller core with performance comparable to that of 16-bit MCUs. The TLCS-870/C1 core can process one instruction in a single clock cycle, enabling faster processing at lower frequencies, reduced noise, and lower power consumption compared with the company’s previous 8-bit cores.
The core has a large-capacity address space that’s expandable to 128 kbytes. It’s well suited for a wide range of jobs, from small-scale applications like portable devices to large-scale applications requiring large-capacity ROM, such as air conditioners, washing machines, and other white goods.
The expanded address space was attained with a memory-management method that manages code and data in separate areas. Up to 128 kbytes of address space can be implemented in an 8-bit MCU without any adverse consequences. Such consequences could include increased footprint due to address-bus expansion or degraded processing speed, which is common with the alternative memory-bank method.
The new core family helps reduce system cost by integrating must-have features such as a voltage-detection circuit, a power-on reset circuit, and an on-chip debug circuit. The TLCS-870/C1 core is binary compatible with previous Toshiba 8-bit MCUs, so existing software resources can be used.
TAEC plans to introduce its first new products based on the new core in the fourth quarter of 2006.
Toshiba America Electronic Components
http://chips.toshiba.com