Finer features and architectural enhancements let the latest-generation FPGAs deliver higher gate counts and application-targeted resources to implement complex systems-on-a-chip.
The rules of the ASIC game are changing as the cost to fabricate a custom solution creeps past the million-dollar mark. And, new rules are emerging due to the shorter market life of the end system and the continuous need to upgrade or update a product's features. The flexibility of FPGAs to meet these changes hits home at the FPGA's heart—its programmable architecture.
In addition, the old concept of an FPGA being just a collection of configurable gates and programmable interconnects has given way to resource-rich platforms. These new FPGAs contain dedicated but configurable high-speed I/O ports capable of multi-gigabit/s data rates, large blocks of single and multiported memories, phase-locked loops (PLLs), multiplier-accumulators (MACs) for DSP support, 32-bit CPUs, and other dedicated functions. And this is just the beginning (see "FPGAs Enter New Design Territory," p. 78).
To integrate those resources, the companies designing the FPGAs employ advanced processes that reduce feature sizes to just 90 nm. Thus, they can pack more gates on a chip while improving gate performance. In addition, these advanced processes use as many as 11 levels of copper metallization to provide better signal routing and configurability.
Device cost is always a key factor for FPGAs, especially those used in the final version of a product. The high-density, resource-rich, top-of-the-line FPGAs tend to cost several hundred dollars to over a $1000 apiece, even in moderate volume. These are used sparingly in production systems and replaced, where possible, with a full ASIC or one of the new structured or platform ASIC alternatives (see "Structured ASICs Compete With, And Complement, FPGAs," p. 81).
New classes of FPGAs with slightly fewer gates, less memory, and a limited number of other features have sprung up, though, to meet the cost constraints of production systems. This will push the crossover point when it makes more economic sense to switch to an ASIC much further out. In some cases, it may never be economical to use an ASIC, because product life cycles are now shrinking below the time required to develop the ASIC replacement.
YOUR PAD OR MINE?
Typically, as gate counts go up, so does the number of I/O pads to move the signals on and off the chip. Today's FPGAs come with hundreds to nearly 1000 I/O pads. Most are housed in very large BGA packages and use traditional wire-bond connections to connect the chip's pads to the package. Yet as operating speeds accelerate and the number of I/O pads increases, traditional wire-bonding schemes fall short in getting the chip to deliver top performance due to inductance and parasitic losses. Furthermore, wirebonding may also make the chip too large for the desired gate count.
These issues arise because traditional design approaches arrange the I/O pads around the chip's perimeter. Consequently, the physical chip size may actually be determined by the number of pads and how tightly they can be spaced. Designers then would fill in the area within the perimeter with as many configurable cells, memory, and other resources as possible.
But this forces system designers to route all high-speed signals to the edge of the chip, which could detract from overall performance of the function being implemented. For large I/O pad counts, chip sizes may expand more than necessary because pad-to-pad spacing must accommodate the automatic wire-bonding machines.
Staggered pad rings offer one partial solution. Pads are actually arranged in two concentric rings, with one ring offset from the other so that the pads in the inner ring reside in the space between the two pads in the outer ring.
Another emerging approach eliminates wire bonding outright, as well as all of the limitations imposed by pad rings. The flip-chip assembly approach, which uses solder-bump connections across the chip's surface, is already employed by a number of companies producing high-performance ASICs.
The flip-chip approach provides several advantages. First, it eliminates the need for a pad ring, considerably reducing chip area. Second, it allows the I/O pads to be more optimally placed right in the middle of the configurable logic array, which shortens the signal paths and reduces inductance and capacitive loading. Although a slightly more expensive packaging technology, the surface-bumped flip-chip approach will be deployed for the highest-performance and highest-I/O-count FPGAs, allowing vendors to charge a premium price for the chips.