While the availability of such IP frees ASIC designers from some detail work, individual cores don’t represent a major fraction of the total design. That fraction declines as designs grow to fill the space available with new process generations. Consequently, the design task gets more difficult with each process generation.
ESL METHODOLOGIES ON THE FAR HORIZON • In light of those reports, there’s still some cause for optimism. Tool vendors increasingly look to electronic-system-level (ESL) design to simplify the creation of ASICs that can fully utilize the transistor counts available from emerging process generations. The ESL approach would allow ASIC developers to create their designs at a higher level than stitching together IP blocks.
According to Frank Schirrmeister, director of product management at Synopsys, several essential requirements for an industry-wide shift to ESL methodologies are already in place. Schirrmeister pointed out, for example, that the use of SystemC to describe chip designs at a transaction level is already occurring, although it’s primarily used today by software developers as a validation target.
A new SystemC TLM2 specification helps standardize transaction abstractions to support the interoperability of tools using SystemC. Schirrmeister also noted, though, that other capabilities still need to be in place before hardware design can switch over, including register-transfer-level (RTL) synthesis tools utilizing a subset of SystemC and tools for equivalence checking between SystemC and RTL designs. Such tools are under active development or in their first commercial incarnations, says Schirrmeister, so the shift to ESL methodology seems inevitable.
Another hope comes from a shift in what ASIC developers seek to gain as they migrate to new processes. According to Open Silicon’s Baldwin, designers today are less interested in ever-increasing performance and more interested in adequate performance at an optimum power point.
This shift, Baldwin explains, parallels the change in the computing industry where faster clocks have given way to increased parallelism. As this paradigm shift takes hold in the market, the slowdown in performance gains of new processes becomes a moot point.
The shift in interest away from absolute performance additionally helps ASIC designers by opening an opportunity to handle process variability. This variability makes some chips faster with higher leakage and other chips slower with lower leakage. Normally, sorting would reject a substantial number of chips for inadequate performance or excessive power. If top performance isn’t required, however, such chips can be salvaged rather than scrapped.
The trick is to apply a bi-directional adaptive body bias (ABB) to the chip. The transistors in a CMOS ASIC are four-terminal devices: drain, source, gate, and body (Fig. 3). Typically, the body connection ties to ground. But researchers at Intel discovered that biasing this connection can shift the performance of a device either way depending on bias polarity.
Slow devices can run faster (with greater leakage), and fast devices can slow down and reduce leakage. This ability to shift performance on a chipby- chip basis can help counter process variability and increase yields in designs targeting the middle of the range.
For the remainder of the decade, then, ASIC designers can expect the trends of continual new process adoption and ever-increasing performance to falter. In their place will be more opportunities to choose a process point based on adequate performance, optimized power, and minimal cost. The trends will return in a few more years as design techniques shift to ESL approaches and techniques such as ABB arise to address the increasing process variability.