Since their introduction in 1984, Field Programmable Gate Arrays (FPGAs) have given designers substantial flexibility and time-to-market advantages compared with ASICs. However, in recent years FPGAs have hit a wall. FPGAs’ great strength, reconfigurability, is unfortunately also the cause of a large weakness — low performance — which keeps FPGAs from competing with ASICs despite the use of smaller technology nodes. As a result, traditional FPGAs have been prevented from playing a role in many high-performance systems where ASICs still dominate, even in low-to-medium-volume applications where an FPGA would be a much more cost effective solution.
The economic and technical forces driving the world of high-performance electronics are leading to frustration with both the ASIC and traditional FPGA approaches. More often, system architects require reprogrammability and short time to market while still satisfying their performance requirements.
This article looks at how an innovative new FPGA architecture signals a break from the nearly three decades of FPGA design in which performance has often been sacrificed for flexibility and time to market. This architecture blends elements of both synchronous and asynchronous architectures, delivering FPGAs capable of exceeding standard-cell ASIC performance.
A NEW FPGA ARCHITECTURE
The new FPGA architecture from Achronix is said to achieve three times the throughput of traditional FPGAs, approaching 1.5 GHz in peak performance. At the heart of this new architecture is the picoPIPE logic fabric (Fig. 1), a fabric that is based on the use of Data Tokens rather than a conventional clocked structure. This high-performance fabric is surrounded by a conventional I/O frame of configurable I/Os, SerDes, clocks, PLLs, etc., providing the off-chip interfaces and forming the boundary between the picoPIPE core and these interfaces. All data entering and exiting the core must pass through the frame. From a designer’s perspective, the internal picoPIPE fabric is virtually indistinguishable from a conventional FPGA fabric — the only distinction is that the data throughput is substantially increased.
In conventional logic, a Data Token is a logic value which is qualified by a clock edge. With a traditional logic implementation, data is always present but is only valid (and therefore propagated though storage elements) when a clock edge is received at a storage element. Hence every time data is propagated from one storage element to the next, only a distinct and valid data value is propagated. The combination of Clock and Data can therefore be implicitly considered as a Data Token. For each register (storage element) in a design that has a clock, there will be a Data Token propagated at every clock tick.
In an Achronix FPGA, the picoPIPE fabric uses explicit Data Tokens rather than implicit ones. Wherever there was an implicit data token in the original design, it will be replaced with an explicit Data Token once the design is mapped into the picoPIPE fabric. As explicit Data Tokens are used, the clock information is encoded into the Data Token – the fact that a token exists at all indicates that a clock edge has occurred. Because each Data Token contains both Data AND Clock information, no global clock is required within the fabric. Data Tokens are still clocked into and out of the fabric using special elements in the frame. The explicit Data Tokens are controlled by fast, local handshaking rather than a global clock, hence are able to propagate at very high speeds.
The basic elements of a picoPIPE (Fig. 2) fabric are the Connection Element (CE), the Functional Element (FE), the Boundary Elements (BEs), and the pipeline stage. Pipeline stages (Fig. 3) connect CEs, FEs, and BEs to form pipeline networks. Once combined into networks, the picoPIPE implementation exactly matches the functionality of conventional FPGAs but is capable of much higher throughput.