Bulletproof Your System Timing With Programmable Clocks

Other examples of using a programmable clock to validate system timing or save power include programming the PLL to operate with higher or lower long-term jitter (LTJ). LTJ is the variation in time between clock edges separated by N clock cycles. A common value for N is 1000. Figure 2 shows the same output of the SL15300 programmed for two different LTJ extremes. It’s particularly important for clocks used as video references to avoid “wavy” displays and those used to clock transceiver components (e.g., USB and LAN transceivers) to maximize the eye diagram opening.

Higher LTJ is achieved by lowering the phase-detector rate, bandwidth, and/ or voltage-controlled oscillator (VCO) frequency of the PLL. It’s useful during development to ensure the system has sufficient timing margin. LTJ can then be reduced to the point where all specifications will be met over process corners while consuming minimum power. When power isn’t a primary concern, the longterm jitter can be reduced to the lowest value allowed by the clock technology to maximize system timing margin.

In summary, the timing sensitivities of digital systems aren’t well modeled. Thus, programmable clocks can be used to maximize and validate timing margin during development and ensure timing margin during production. This optimization helps reduce system cost and optimize system performance, including power dissipation.