Careful HDL Coding Maximizes Performance In LUT-Based FPGAs

In an ideal world, synthesis tools would understand and exploit all field-programmable gate array (FPGA) architectures and their special features without designer intervention. In the real world, however, this isn't the case. Applications that are speed- and area-intensive require that designers be aware of the consequences of coding style. To obtain optimal results, an understanding of the FPGA's architecture, the synthesis tool, and the back-end layout software also becomes necessary.

Most FPGAs are not fine-grained. Instead, they're made up of programmable functional units (PFUs) that implement combinational logic in lookup tables (LUTs) and a certain number of flip-flops or latches. The following lists some FPGA features that synthesis tools may have difficulties implementing:

• The flip-flops inside the PFUs share some control signals, such as the clock, clock enable, and reset/set. In an ORCA architecture, for example, four flip-flops will fit inside a single PFU only if they have the same mentioned signals. Most synthesis tools don't understand this. If a design is coded without keeping this fact in mind, the tools might utilize some of the flip-flops inefficiently. This results in an inflated chip size.
• Memory elements inside some FPGAs can be implemented in the LUT portion of the PFU. This method of constructing RAM or ROM inside FPGAs saves a large number of gates and drastically improves the speed of a device. Unfortunately, there's no one way to implement memory in HDL. Hence, the synthesis tools can't detect their presence to utilize the FPGA's LUT feature.
• Counters and state machines also are difficult. With so many different kinds of these circuits, the reason for using one over another is mostly dependent on the application. A knowledge of an FPGA's architecture also helps in deciding which method is most efficient.
• Design hierarchy and floorplanning is hard for synthesis tools to implement.
• Global Set Reset (GSR) signal is an internally routed reset signal that doesn't consume any of a chip's routing resources. There's currently no way to implement this feature in VHDL. Consequently, synthesis tools can't utilize this feature unless the GSR component gets instantiated in the HDL code.

There are three basic techniques for writing VHDL code. Starting with the least efficient method, they are:

1. A generic code that has not been targeted to an architecture.
2. A generic code targeted towards a device architecture.
3. An HDL code with macro instantiation.

It helps to compare these three methods, incorporating coding styles that would be targeted to reduce the aforementioned synthesis inefficiencies.

Synchronous Logic
Flip-flops and latches in most LUT-based FPGAs can be configured in synchronous set/reset mode using the Local Set Reset (LSR) assigned by the designers. In order for a latch or flip-flop to be implemented correctly, the synthesis tool must instantiate the proper library macro. But, this won't happen unless the HDL code contains the correct description. A basic understanding of the FPGA architecture to be used is a must.

Designers have to keep in mind the kinds of flip-flops and latches that are available in the vendor's macro library. If the code implements a register functionality that's not represented by a corresponding macro in the library, the extra functionality will be added to the circuit using additional logic. Most of the time, this extra logic ends up on the registers' datapath, increasing area and delay.

Each PFU can implement up to a certain number of latch and/or flip-flops that share some of its inputs. To get the highest area utilization out of the device, latches and flip-flops are best grouped in multiples of the PFU's register capacity.

If synchronous functionality of the flip-flops is required, the Global Set Reset signal can't implement the set/reset signal. This is because the GSR has asynchronous functionality. It can, however, be used in addition to the LSR signal.

If the code implies a gated Clock Enable (CE) signal, the synthesis tool tends to duplicate the enable logic for every register in the design. To avoid this, it's recommended to keep the gated signals in a separate process. Also, pass their output to the CE input of the main module.

In order to use the correct flip-flop, the HDL code has to describe the correct functionality. For instance, the following code listing is used to implement a two-bit register with a +V_E level synchronous reset and a +V_E level enable signal.

DO <= D1 AND D2;
SYNC_RST : Process (CLK,RST)
begin
if (CLK'event and CLK='1') then
if (RST = '1') then
DATA_OUT <= (others => '0');
elsif (DO = '1') then
DATA_OUT <= DATA_IN ;
end if;
end if;
end process SYNC_RST;

Note that to implement a synchronous reset correctly the "if (RST = '1') then" statement has to be entered after the CLK'event inside the process. And for "DO" to be connected to the CE input of the flip-flop, the "elsif (DO = '1') then" statement must go after the "if (RST = '1') then".