The high cost of developing an ASIC in a 90-nm process, typically estimated between $15 million and $20 million, makes many companies think twice about whether a full-custom solution is economically viable. When a design doesn't work properly after initial fabrication, the cost of fixing errors and redoing the masks, plus the time lost to prefabricate the chip, bloats overall development time and cost.
TRIMMING HIGH ASIC COSTS
To counter spiraling costs, vendors are developing partially remanufactured solutions called structured and platform ASICs. Fundamentally, these solutions leverage the basic precept of the gate array, but they offer much more as a starting point. Typical resources offered on the structured and platform chips include blocks of RAM, phase-locked loops, high-speed I/O buffers, and multigigabit serializer/ deserializer ports.
Today, most structured and platform offerings are implemented with 130-nm processes. But a few companies, such as LSI Logic and Fujitsu, squeeze the design rules down to 110 and 90 nm, respectively, for their highest-performance offerings.
Because the silicon is remanufactured, and the pre-integrated functions are verified, designers need only create the metal interconnect definition for their circuit functions. Then, the final few metal masks can be prepared to complete the manufacturing process. This considerably lowers the final nonrecurring-engineering costs for design verification and mask creation. It also shortens the turnaround time from design handoff to samples.
But the chips aren't custom-crafted, so they tend to be slightly larger than a potential full-custom implementation of the same logic—and perhaps, not quite as fast. The larger chip size often translates into a higher per-chip cost than a custom ASIC, especially if the ASIC will be produced in large quantities.
As the cost of developing a full ASIC continues to soar, so does the popularity of structured and platform solutions. Over two dozen large and small companies compete in this market. They offer solutions that use customization schemes ranging from direct electron-beam patterning for mask-less final configuration to about five levels of metallization to configure logic fabrics based on a fine-grained logic building block.
The broadest set of platform ASIC offerings continues to come from LSI Logic, with its nearly two dozen configurations. These chips also make a good transition solution for many designs initially implemented in an FPGA, which are now ready for some level of volume manufacturing.
LIBRARY UPDATES CRITICAL
Key to the timely deployment of any ASSP or ASIC is the ability to exploit available IP that will reduce the SoC's design time. To encourage IP use, ASIC suppliers and foundries continue to build their IP libraries and partnerships with various IP suppliers to further expand the building-block options.
CPU cores ranging from 8-bit controllers (e.g., 8051s) to 32-bit architectures (e.g., ARM7 and ARM9), as well as the ARC and Tensilica cores, have been available. But expect many next-generation cores to significantly improve performance. Some of these cores include ARM's ARM11 and Cortex-A8, as well as enhanced CPU cores from ARC and Tensilica. They will sate the demand for ever-higher throughput.
Upcoming blocks of IP include DDR2 memory controllers, H.264 video encode/ decode blocks, PCI Express interfaces, and other blocks targeting the audio/ video and consumer markets.
Design support for cores comes in the form of standard buses and standardized logic interfaces (sometimes called wrappers). Such support has made its way through standard organizations such as the VSI Alliance, the Silicon Integration Initiative, and the European Electronic Chips and Systems Design Initiative. These groups are hard at work developing SoC, IP, and reuse standards, which will ultimately enhance the productivity of SoC designers.