When it comes to FPGAs, it’s never been more exciting than it is right now. The wide range of choices from platforms to tools to soft-core processors has never been larger. Flash FPGAs can target applications that once were the realm of only low-power microcontrollers, while high-performance 28-nm FPGAs can beat out the fastest processors on the market for many applications.
Arm hard-core processor use is on the rise. The Cortex-M3 is found in Actel’s SmartFusion FPGA (see “FPGA Combines Hard-Core Cortex-M3 And Analog Peripherals”). It joins a wide range of soft-core processors like the Cortex-M1 (see “Actel/ARM Develop 32-Bit Processor For FPGAs”), the popular 8051, and Freescale’s ColdFire V1 (see “Cold, Dense, And Gratis MCU Core Targets FPGAs”).
On the other hand, there are processor cores specifically designed for their host platforms like Altera’s NIOS II (see “Latest NIOS CPU Targets 32-Bit Control Needs”) and Xilinx’s MicroBlaze (see “FPGAs Pushing MCUs As The Platform Of Choice”). More designs are utilizing these kinds of platforms, and multicore designs are becoming more common.
Folding FPGAs
FPGA platforms have seen a couple of twists recently. For example, the Achronix Speedster has pushed the envelope when it comes to speed (see “1.5-GHz FPGA Takes Clock Gating To The Max”). It incorporates picoPIPE interconnects between lookup-table (LUT) blocks (Fig. 1). These asynchronous first-in, first-out (FIFO) connections allow the top clock speed to be limited by the delay of a single LUT instead of the LUT chain of logic between latches of conventional FPGA designs. The Speedster targets high-performance applications.
Tabula’s ABAX uses a dynamic reconfiguration approach by design where the underlying fabric can change every clock cycle (see “FPGAs Enter The Third Dimension”). The ABAX TimeSpace architecture provides latches to retain the system state between transitions (Fig. 2).
Each transition changes the underlying interconnect, providing a new FPGA layout for each state or layer. Each region can have up to eight layers with the last providing state information to the base layer. If all eight layers are used, then the amount of logic available to the designer is eight times that of the base chip.
The ABAX architecture supports multiple regions (Fig. 3). This allows the number of layers and the cycle time for each region to be different. The cycle time of a region affects power consumption, with a lower cycle time using less power.
28 nm: The Cutting Edge
Xilinx and Altera have announced their 28-nm technology. It is in the hands of select users but will be generally available in 2011. As usual, the chips are faster, have more LUTs, and use less power per LUT. They also stretch the limits of serializers/deserializers (SERDES) at the high end.
Altera’s Stratix V GT is pushing 28-Gbit/s SERDES to support optical modules. The Stratix V GX’s SERDES run at 12.5 Gbits/s, and they are designed to handle 10G standards such as 10-Gbit Ethernet.
Continue to next page