As data transfer rates increase and system integrators strive to bring more services and features to the communications systems they're crafting, current-generation communications processors are running out of steam. Future enterprise routers, media gateways, wireless basestations, and multiservice access platforms must offer new services, greater flexibility in their system configurations, and an overall lower price per port.
To meet these system needs, designers at Motorola have developed their fifth-generation series of communications processors, the PowerQUICC III family. The first family member, the MPC8560, provides a highly integrated solution that gives designers dual triple-speed Ethernet ports capable of 10/100/1000-Mbit/s data rates and layer 2 acceleration. It employs a high-speed 32-bit PowerPC CPU based on the e500 core, which can operate at 600- to 833-MHz and higher clock speeds. It also has an enhanced communications processor module (CPM) that runs at 333 MHz, or about 50% faster than the previous-generation CPM on the PowerQUICC II processors (see the figure).
The processor actually packs many more enhancements and features. For example, to improve system expandability, designers equipped the PowerQUICC with a RapidI/O interface, a 64-bit PCI bus controller, and a 333-MHz double-data-rate DRAM controller. The low-pin-count 8-bit Rapid-I/O interface employs LVDS signaling and allows data transfers to take place between two chips at a peak data rate of 8 Gbits/s in each direction. Multichip systems can also be implemented by using RapidI/O bus switches.
Besides adding these new features, designers maintained backwards CPM software compatibility. That allows systems built with the previous-generation PowerQUICC II chips to be upgraded without massive software updates.
In comparison to the forthcoming MPC8560, most of today's integrated silicon solutions are too slow to handle the gigabit data streams and the complex control/analysis tasks required on those high-speed streams. Or else, they don't provide the level of integration to deliver a cost-effective system solution.
To match the PowerQUICC III's level of functionality, today's system designers would have to use discrete building blocks—an 833-MHz RISC CPU, multiple Gigabit Ethernet interfaces, specialized communications blocks for handling ATM and TDM interfaces, and much more. Such a discrete solution would occupy significantly more board space, consume much more power, and take lots of custom software to make all the blocks play together.
Integrating all key building blocks on one MPC8560 provides a system-on-a-chip solution that can scale with the performance needs of systems for many years. Simultaneously, the design permits future extensions through an on-chip, nonblocking, crossbar connection fabric called OCeaN (On-Chip Network). This fabric offers a 22-Gbit/s per-port peak bandwidth in each direction in addition to independent transaction queuing and flow control.
A dual-issue superscalar CPU, the high-performance e500 processor core achieves a throughput of 1850 MIPS when clocked at 800 MHz. This high-throughput processor enables the PowerQUICC III to handle many functions that previously required the host CPU, potentially eliminating the need for a host CPU. By shifting the forwarding plane processing to the CPM, designers can also unburden the e500 core, leaving it free to perform higher-level system functions.