Several practical issues must be addressed when designing the clock tree for a system running synchronously at high speed. First is the signal integrity of the clock itself, i.e., maintaining low jitter and low distortion all the way to the receiver. Second is controlling clock interference with other parts of the system, as well as compliance with electromagnetic- interference (EMI) regulations.
These issues are easy to understand, but hard to practice without proper guidelines. Practical solutions are available, though, and many methods can be applied to any high-speed design.
MINIMIZE CLOCK SIGNAL DEGRADATION
There are two major effects to consider when distributing a high-speed clock: trace attenuation and reflection.1 Even though the clock speed might not be high, its rising and falling edge needs to be sharp for low-jitter performance.
From a spectrum point of view, the edge consists of many highfrequency harmonics. The board trace material is lossy, acting like a low-pass filter. The amount of attenuation is more severe as the frequency goes higher and the trace gets longer.
When the signal arrives at the receiver, different frequency components are attenuated differently, distorting the edge and increasing jitter. This is trace attenuation. There’s little one can do to counter this issue, other than choose high-swing mode when attenuation dominates.
Reflection is a bigger problem for clock distribution. Figure 1 shows simulation results with an unterminated trace. The driver output impedance is at 25 Ω, and the characteristic impedance of the trace is 50 Ω. The receiver has high-input impedance.
The ideal signal is the green signal with 3.3-V swing at 45 MHz. The blue signal is the signal at the driver’s side, and the red signal is the signal at the receiver’s input. Maximum voltage at the trace end is approximately 4.4 V instead of 3.3 V, and the minimum voltage is approximately –1 V instead of 0 V.
Reflection due to impedance mismatching when there’s no termination causes this obvious overshoot and undershoot. Such a circumstance can damage the I/O of the driver and receiver. Therefore, minimizing reflection is the most important task for clock distribution. The key is to properly terminate the trace.
There are multiple ways to terminate a transmission line. But for clock distribution, the most common methods are perhaps series termination, parallel termination, Thevenin termination, and ac termination. Only series termination is done at the driver side. The other three eliminate the reflection at the receiver end.
Series termination involves directly connecting a resistor in series with the driver output pin and the trace (Fig. 2a). The value of the series resistor is chosen so its sum plus the output impedance of the driver equals the characteristic impedance of the transmission line (ZO). In most designs, a value of R = 25 to 30 Ω is recommended and can be determined by measurement.
Series termination is chosen when the driver output impedance is smaller than ZO. For most transistor-transistor logic (TTL) or low-voltage CMOS (LVCMOS) drivers, this is the case. Series termination also has no dc current to ground, so it is a low-power solution. But the rise/fall time slows down and, thus, there’s less jitter immunity. The TTL or LVCMOS driver should drive a small number of devices located at the far end.
Parallel termination is when a resistor is connected at the end of the trace to ground, in parallel to the input circuitry of the receiver (Fig. 2b). It’s simple but consumes the most power of all four methods.
For Thévenin termination, two resistors are connected in series from power to ground at the end of the trace (Fig. 2c). It consumes less power, but requires two components.
The most commonly used sink termination method for clocks is ac termination, since it doesn’t consume dc power (Fig. 2d). Yet with an added capacitor, propagation delay is larger. The resistor values are usually chosen to be larger than 50 Ω to counter the leakage to the input stage of the receiver.
For example, 75 Ω is typically used. The capacitor value should be bigger than 50 pF to effectively sink ac current. A higher capacitor value enables heavier ac sink, but consumes more power. Also, to ensure decent transition edge of the clock, a value between 100 and 120 pF is recommended.
All of these methods can be applicable to different scenarios. Choose wisely, keeping the above pros and cons in mind, and experiment.
Continue to page 2