The advent of programmable logic has given designers nearly infinite flexibility in implementing digital logic designs. However, with the flexibility afforded by these devices, some common design practices may get overlooked. Often, the speed in which today's tools can take a design from specification to implementation leads to numerous trial-and-error attempts to get the design to work. In haste, engineers might end up with a design that contains asynchronous circuits in places where synchronous circuits could be used. Because flexible parts are used to implement the logic, the designs easily fit to the parts with the asynchronous logic intact.
This article will discuss the advantages of synchronous circuits over asynchronous circuits, and will also present common rules for designing good synchronous circuits. Lastly, we'll look at some circuits that contain asynchronous behavior and provide better synchronous alternatives.
If there were but one rule to follow in digital design it would be to make the design completely synchronous. Using registers that are clocked by a single common clock leads to the best overall system designs for a variety of reasons.
First of all, synchronous designs are more reliable. They are deterministic in their behavior, due to the fact that all signals are sampled at a well-defined time interval. Synchronous designs rely on very few timing parameters to guarantee operation, namely, the maximum frequency of operation of a device (fmax), the register setup and hold times (tSU and tH), and the register clock-to-output time (tCO). Meeting these parameters ensures designs will work under temperature, voltage, and process variations.
Synchronous designs are also portable. In all PLDs and ASICs, the master clock, or clocks, are routed via a low-skew clock network. These networks ensure that a design done in one PLD architecture will be compatible with a different architecture, with good results. Synchronous designs take advantage of this trait.
In addition, synchronous designs can be tested more easily and run statically, with the clock input driven by a test signal. They can be made virtually immune to noise. Therefore, finding errors in a design will not be a cross between identifying logic errors and tracking down noise-induced errors.
Synchronous designs attain performance levels easily. The maximum operational frequency of a synchronous design can be determined from the data sheet for many PLDs. Determining maximum performance of circuits that include asynchronous clocking events is much more complicated.
Finally, synchronous designs are easier to code in a hardware description language (HDL), and are also easier to read. Designs built around a common clock yield compact, efficient code. On the other hand, designs with numerous clocks and asynchronous behavior are more difficult to understand. Their code descriptions can also get cumbersome.
Synchronous Rules To Live By
All inputs to a synchronous circuit need to be synchronous. If an asynchronous input to a synchronous circuit violates the tSU or tH of the registers, some of the registers may resolve the input as a logic 1, while others resolve it to logic 0. The classic way to synchronize asynchronous signals is to drive the signal through two cascaded D flip-flops.
Most PLD architectures guarantee a very high mean time between failure (MTBF) with this type of circuit, up to the fmax specification on the device data sheet. The MTBF, in this sense, is a statistical value that measures how often, on average, the second register in the synchronizer will receive an input that is not yet resolved by the first register. For example, the Cypress Flash370i and Ultra37000 families of CPLDs guarantee a 10-year MTBF for this type of circuit. This circuit is designed into the input macrocells of the device. Thus, the output of the second register will provide a signal that is synchronous to the rest of the logic.
When a design relies on more than a single clock, and information needs to be transferred from one clock domain into the other, the interaction must be treated as an asynchronous event—unless there's a known phase and frequency relationship between the clock domains. If many signals need to be transferred, a single synchronized handshake signal from the source-clock domain to the receiving domain should be used. When the handshake signal is received, the remaining signals can be captured from the source side. Those remaining signals should be sent across without synchronization. This guarantees that they have enough settling time to meet the tSU for the clock in the other domain.
Every asynchronous external signal input to a finite state machine (FSM) must be synchronized (with the two flip-flop synchronizer) to the FSM's clock to ensure appropriate behavior. Imagine the chaos that would result if a signal were to be left asynchronous and, while the input was in transition, some of the FSM's state registers detected a logic low while others detected a logic high.
It's just as important to keep outputs from an FSM synchronized. FSM outputs can be used for such functions as counter enables, register enables, and output enables. In any of these cases, the signal integrity is best when kept synchronous with the FSM's clock. This prevents unwanted propagation delays and possible glitches when the FSM transitions between states.
In many cases, engineers insert buffers and inverters in their designs to create an artificial delay. Too often, these delays are used to fix bad design techniques, such as using a register output to drive the clock input of another register. The delay might be put in the clock path to ensure that data arrives at the register before the clock does. The problem with adding delays is that the delay time is always unpredictable. What works today might not work if the design is ported to another device. The temperature differs, the process used for the device changes, the version of the logic synthesizer changes, and so on.
The advent of programmable logic has given designers nearly infinite flexibility in implementing digital logic designs. However, with the flexibility afforded by these devices, some common design practices may get overlooked. Often, the speed in which today's tools can take a design from specification to implementation leads to numerous trial-and-error attempts to get the design to work. In haste, engineers might end up with a design that contains asynchronous circuits in places where synchronous circuits could be used. Because flexible parts are used to implement the logic, the designs easily fit to the parts with the asynchronous logic intact.
This article will discuss the advantages of synchronous circuits over asynchronous circuits, and will also present common rules for designing good synchronous circuits. Lastly, we'll look at some circuits that contain asynchronous behavior and provide better synchronous alternatives.
If there were but one rule to follow in digital design it would be to make the design completely synchronous. Using registers that are clocked by a single common clock leads to the best overall system designs for a variety of reasons.
First of all, synchronous designs are more reliable. They are deterministic in their behavior, due to the fact that all signals are sampled at a well-defined time interval. Synchronous designs rely on very few timing parameters to guarantee operation, namely, the maximum frequency of operation of a device (fmax), the register setup and hold times (tSU and tH), and the register clock-to-output time (tCO). Meeting these parameters ensures designs will work under temperature, voltage, and process variations.
Synchronous designs are also portable. In all PLDs and ASICs, the master clock, or clocks, are routed via a low-skew clock network. These networks ensure that a design done in one PLD architecture will be compatible with a different architecture, with good results. Synchronous designs take advantage of this trait.
In addition, synchronous designs can be tested more easily and run statically, with the clock input driven by a test signal. They can be made virtually immune to noise. Therefore, finding errors in a design will not be a cross between identifying logic errors and tracking down noise-induced errors.
Synchronous designs attain performance levels easily. The maximum operational frequency of a synchronous design can be determined from the data sheet for many PLDs. Determining maximum performance of circuits that include asynchronous clocking events is much more complicated.
Finally, synchronous designs are easier to code in a hardware description language (HDL), and are also easier to read. Designs built around a common clock yield compact, efficient code. On the other hand, designs with numerous clocks and asynchronous behavior are more difficult to understand. Their code descriptions can also get cumbersome.
Synchronous Rules To Live By
All inputs to a synchronous circuit need to be synchronous. If an asynchronous input to a synchronous circuit violates the tSU or tH of the registers, some of the registers may resolve the input as a logic 1, while others resolve it to logic 0. The classic way to synchronize asynchronous signals is to drive the signal through two cascaded D flip-flops.
Most PLD architectures guarantee a very high mean time between failure (MTBF) with this type of circuit, up to the fmax specification on the device data sheet. The MTBF, in this sense, is a statistical value that measures how often, on average, the second register in the synchronizer will receive an input that is not yet resolved by the first register. For example, the Cypress Flash370i and Ultra37000 families of CPLDs guarantee a 10-year MTBF for this type of circuit. This circuit is designed into the input macrocells of the device. Thus, the output of the second register will provide a signal that is synchronous to the rest of the logic.
When a design relies on more than a single clock, and information needs to be transferred from one clock domain into the other, the interaction must be treated as an asynchronous event—unless there's a known phase and frequency relationship between the clock domains. If many signals need to be transferred, a single synchronized handshake signal from the source-clock domain to the receiving domain should be used. When the handshake signal is received, the remaining signals can be captured from the source side. Those remaining signals should be sent across without synchronization. This guarantees that they have enough settling time to meet the tSU for the clock in the other domain.
Every asynchronous external signal input to a finite state machine (FSM) must be synchronized (with the two flip-flop synchronizer) to the FSM's clock to ensure appropriate behavior. Imagine the chaos that would result if a signal were to be left asynchronous and, while the input was in transition, some of the FSM's state registers detected a logic low while others detected a logic high.
It's just as important to keep outputs from an FSM synchronized. FSM outputs can be used for such functions as counter enables, register enables, and output enables. In any of these cases, the signal integrity is best when kept synchronous with the FSM's clock. This prevents unwanted propagation delays and possible glitches when the FSM transitions between states.
In many cases, engineers insert buffers and inverters in their designs to create an artificial delay. Too often, these delays are used to fix bad design techniques, such as using a register output to drive the clock input of another register. The delay might be put in the clock path to ensure that data arrives at the register before the clock does. The problem with adding delays is that the delay time is always unpredictable. What works today might not work if the design is ported to another device. The temperature differs, the process used for the device changes, the version of the logic synthesizer changes, and so on.