Many generic cores may be purchased directly for our products with a common interconnect. Or, an off-the-shelf third-party core can be "wrapped" with the necessary logic to package the signals used by the off-the-shelf core into the common interconnect (Fig. 3). Typically, the wrapper logic is straightforward to implement, and once the wrapper is completed, the third-party core can then be reused in multiple applications.
Application-specific functions can be implemented in any desired tool chain, again using wrappers to encapsulate the application processing inside a standard framework. As with third-party cores, the application-specific functions can easily be reused via this approach.
Once the cores are implemented, the application must be mapped into actual hardware. With today's products, the input may arrive using PMC-based I/O modules and traditional PCI bus implementations (Fig. 4a). Such an implementation employs three FPGAs, one on the I/O module and two on the carrier card, to perform the required functions. The data transport between FPGAs uses PCI (from A to B) and RACE++ (from B to C and C to D) endpoint IP cores with common interconnect.
Future platforms will support higher-speed interconnects, replacing PCI bus with PCI Express, and RACE++ with PCI Express, RapidIO, or other switched-fabric interconnects. A PCI Express implementation with two FPGAs is shown in Figure 4b, and Figure 4c depicts a higher-density solution using a single FPGA and RapidIO. In all cases, the IP cores developed for the application are reused without modifications. Only the top-level design must be changed.
Will On-Chip Standards Emerge?
The interconnect architecture described above is our implementation of a cross-platform, cross-fabric, cross-technology strategy for protecting IP investment. Although designed to be general purpose, it's implemented on one company's products and is therefore not an open standard.
There are standards available on the open market to meet a wide range of requirements for IP-to-IP interconnect. Many of the standards are designed for processor bus implementations, making them too resource-intensive for high-performance embedded applications. Other standards have been defined by specific FPGA manufacturers, resulting in solutions that aren't portable across different FPGA solutions. To date, though, an open portable solution that meets the needs of the marketplace has yet to emerge. It remains to be seen if any current standards will achieve the critical mass necessary to become a de facto open standard. Unlike board-to-backplane hardware interfaces, FPGAs are inherently adaptable, and IP cores written to different standards can be adapted to work together. This reduces the pressure on vendors to invest in the type of open, industry-wide standards that are required for board-level products.
Fortunately, most benefits of modularity and reuse can be achieved whether or not the selected interconnect becomes widely available. By using a modular architecture and building IP cores based on common interconnects, system designers can focus development investment on the value-added parts of the solution, maximize design reuse, and reduce the schedule and development costs of technology changes in the future.