Digital Current-Mode Control Challenges Analog Counterparts

DSCs with the appropriate peripherals can implement current-mode control in digital SMPSs. Many possible methods exist for performing current-mode control when implementing an SMPS design with a DSC. In the digital current-mode approach, the key is use of a DSC with an on-chip PWM peripheral that works in the same way as a standalone current-mode PWM generator (Fig. 6).

Two mixed-signal components, a voltage comparator and a digital-to-analog converter (DAC), are added to a normal, timer-based PWM peripheral (Fig. 7). The voltage comparator supplies a shutdown signal to the PWM module, which is gated together with the output of the duty-cycle counter. When the duty-cycle counter reaches zero, the comparator output can drive the PWM output to zero.

The DAC receives its input from the DSC and generates a reference signal into the comparator. When the system is integrated into a digital SMPS, the counters in the PWM module start the PWM pulse, the DAC generates a voltage at the inverting input to the comparator representing the inductor's desired current, and the current feedback feeds into the comparator's non-inverting input.

As the current builds in the inductor, the duty-cycle counter continues to count up. If the inductor current reaches the desired level first, the comparator terminates the pulse and the inductor begins to discharge into the output capacitors. If the PWM counter reaches the specified duty-cycle value first, it terminates the PWM pulse. This provides the best of both worlds—a fast current-mode feedback that doesn't require a high MIPS processor, and the ability to set a maximum duty cycle for current limiting.

IMPLEMENTING DIGITAL CURRENT MODE
To implement a digital current-mode system, begin by determining the PWM frequency and maximum duty cycle required by the SMPS design. These parameters configure the PWM's counter section. Next, scale the reference DAC output to the expected maximum range of the current-feedback signal. This provides the highest resolution when controlling the PWM duty cycle.

Finally, design the proportional integrator differentiator (PID) software code. The code takes the voltage feedback from the ADC, compares it to the internal digital reference, filters it appropriately for stability, and then outputs the desired current setting to the DAC that generates the comparator reference (Fig. 7, again).

To handle current-mode stability problems with duty cycles greater than 50%, the PID software sets the required current level so scaling the DAC value becomes a trivial task. This makes implementing slope compensation in the digital world easier than in the analog world, because it only requires software control. An analog solution requires a ramp generator synchronized to the PWM pulse as well as a summing junction. (In the latter, the ramp adds to the current feedback.)

The result of this process is a simple, current-mode SMPS that uses cost-effective, 30-MIPS DSCs to accomplish what a 1- to 2-BIPS processor does the hard way. This DSC only needs to calculate a new desired current level before the start of the next pulse. As a result, the DSC should have enough free time to accomplish other tasks, such as communications, system monitoring, and deterministic functions that include soft-start/ power-up sequencing and handling fault detection and recovery.

DSCs with the appropriate peripherals can implement current-mode control in digital SMPSs. Many possible methods exist for performing current-mode control when implementing an SMPS design with a DSC. In the digital current-mode approach, the key is use of a DSC with an on-chip PWM peripheral that works in the same way as a standalone current-mode PWM generator (Fig. 6).

Two mixed-signal components, a voltage comparator and a digital-to-analog converter (DAC), are added to a normal, timer-based PWM peripheral (Fig. 7). The voltage comparator supplies a shutdown signal to the PWM module, which is gated together with the output of the duty-cycle counter. When the duty-cycle counter reaches zero, the comparator output can drive the PWM output to zero.

The DAC receives its input from the DSC and generates a reference signal into the comparator. When the system is integrated into a digital SMPS, the counters in the PWM module start the PWM pulse, the DAC generates a voltage at the inverting input to the comparator representing the inductor's desired current, and the current feedback feeds into the comparator's non-inverting input.

As the current builds in the inductor, the duty-cycle counter continues to count up. If the inductor current reaches the desired level first, the comparator terminates the pulse and the inductor begins to discharge into the output capacitors. If the PWM counter reaches the specified duty-cycle value first, it terminates the PWM pulse. This provides the best of both worlds—a fast current-mode feedback that doesn't require a high MIPS processor, and the ability to set a maximum duty cycle for current limiting.

IMPLEMENTING DIGITAL CURRENT MODE
To implement a digital current-mode system, begin by determining the PWM frequency and maximum duty cycle required by the SMPS design. These parameters configure the PWM's counter section. Next, scale the reference DAC output to the expected maximum range of the current-feedback signal. This provides the highest resolution when controlling the PWM duty cycle.

Finally, design the proportional integrator differentiator (PID) software code. The code takes the voltage feedback from the ADC, compares it to the internal digital reference, filters it appropriately for stability, and then outputs the desired current setting to the DAC that generates the comparator reference (Fig. 7, again).

To handle current-mode stability problems with duty cycles greater than 50%, the PID software sets the required current level so scaling the DAC value becomes a trivial task. This makes implementing slope compensation in the digital world easier than in the analog world, because it only requires software control. An analog solution requires a ramp generator synchronized to the PWM pulse as well as a summing junction. (In the latter, the ramp adds to the current feedback.)

The result of this process is a simple, current-mode SMPS that uses cost-effective, 30-MIPS DSCs to accomplish what a 1- to 2-BIPS processor does the hard way. This DSC only needs to calculate a new desired current level before the start of the next pulse. As a result, the DSC should have enough free time to accomplish other tasks, such as communications, system monitoring, and deterministic functions that include soft-start/ power-up sequencing and handling fault detection and recovery.