Design feature size will continue to shrink below 0.13 µm, which will make possible ASICs that pack well over 10 million gates and multiple megabytes of memory. It will also permit chips to achieve system clock speeds of well over 1 GHz, with selective I/O functions able to achieve data transfer rates of up to 5 Gtransfers/s.
Larger, more complex blocks of intellectual property will be available to build system solutions on-chip. Today's 32-bit CPU cores will give way to 64-bit and VLIW processors that can take on ever-more-challenging computational tasks.
Improved standards for core connectivity and on-chip buses will come from the VSIA (www.vsi.org) and other organizations to help simplify the design of chips that pack multiple blocks of IP from multiple suppliers.
More capable EDA tools, from design languages to final layout, routing, and verification, will make possible first-time-right designs that not only meet functional requirements, but also the clock speed demands of future systems.
Expect more extensive use of high-speed serial interface cores for chip-to-chip interconnections and chip-to-system applications such as high-speed serial backplanes and interconnection fabrics such as InfiniBand.
Designers will incorporate larger amounts of on-chip SRAM and DRAM to reduce overall system chip count and maximize memory bandwidth and ASIC performance. By integrating the memory on-chip, designers can use extremely wide memory buses, say 256 to 1024 bits wide, which wouldn't be practical with off-chip memories.
Improved mixed-signal capabilities will be possible, both through the use of standard CMOS processes and by designing with new processes such as silicon-germanium to integrate both digital and RF circuits on the same chip.
Standard-cell design approaches will merge with field-programmable gate-array (FPGA) technology. Programmable blocks on an ASIC speed up chip design, and the last few thousand gates can be configured by downloading the bit pattern into the on-chip FPGA block or blocks.
Increased use of more levels of metallization will improve on-chip connectivity and performance. ASIC designs are starting to migrate away from aluminum interconnects to copper. Production-proven processes, such as chemical-mechanical polishing to planarize the wafer surface, and the ability to deposit copper and low-k dielectric materials, will allow designers to leverage 10 or more metal layers to interconnect tens of millions of gates.
There also is a movement toward lower operating voltages. As the number of gates on a chip increases, so does power consumption. Lowering today's 2.5-V operating voltage to 1.5 V and even lower will grant designers significant reductions in power consumption.
See associated timeline.