Digital ICs: Standard Logic

Shorter propagation delays are in the wings for bus-interface circuits. Today's 2- to 3-ns delays will shrink by close to 50% over the next 12 to 24 months, making possible buffers and translators that operate at speeds exceeding 400 MHz.

Lower standby power levels will become critical as more systems go portable. New circuits will employ clock-gating and signal-sensing schemes to minimize power drain.

Higher-density interface circuits will pack more buffers and latches on a chip to reduce package count on boards.

As operating voltages go down, signal swings get smaller and there's a greater need for LVDS schemes that can handle data rates of 600 Mbits/s and higher.

Expect programmable logic devices and ASICs to continue replacing most general logic functions.

Serial backplane drivers will become more popular as designers try to minimize bus widths and chip pin counts. Today's 2.5-Gbit/s SERDES chips will give way to chips that can operate at 5 Gbits/s.

Expect a wider variety of clock buffering and distribution chips to reduce signal skews and improve system performance.

More high-speed standard serial interface choices will appear—infiniband, hypertransport, and others to meet the need for higher I/O bandwidth.

A continued interest in single-gate packaged logic elements will extend into this decade because these devices provide point solutions to designers in need of a gate here, a flip-flop there, an inverter somewhere else, and so on.

Look also for LVDS to work in multidrop bus structures as opposed to point-to-point connections.

See associated timeline.