When the days were old and the
knights were bold and IP was
invented, you'd wrap an insulator around your gate and leakage was prevented. As the insulator became thinner
with process shrinkages, though, leakage
became a problem. It's so bad, engineers
are now having nightmares about their
future 45- and 32-nm designs.
"Subthreshold and gate leakage have
become a large problems in deep-submicron technologies," says Dan Hillman,
vice president of engineering at Mosaid
Technologies.
Intel, IBM, and Sematech have delivered disparate solutions for the first fundamental change in transistors in nearly
40 years (see "Transistor Recovers From
Midlife Crisis With Fundamental Material Change,"). But what if you
can't afford to partner with IBM?
Consider Mosaid's Mobilize low-power IP platform.
"Mobilize virtually eliminates
leakage, enabling low-power
design in 90 nm and 65 nm without changing the silicon
process," says Hillman.
The platform addresses leakage by providing static and active
power management in a configurable standard-cell library that's used to form voltage- and frequency-scalable power islands ().
An automated hardware- or software-controlled power island manager (PIM)
administers all power island sequencing
of active and sleep phases over process,
voltage, and temperature. This eases the
instantiation of power islands while reducing leakage over 100-fold. It also can be
used in conjunction with 1- and 0.8-V supplies. And, it can transition to and from
sleep mode in a mere 50 ns.
There will be no speed impact using
the Mobilize platform, and the overhead
will require an area increase of less than
2%. Since the technology is built using
standard manufacturing processes, no
architectural changes to existing designs
are required.
Available now, Mobilize is based on
standard cells. It works seamlessly in conjunction with EDA tools from Cadence,
Magma, and Synopsys.
Mosaid Technologies
www.mosaid.com