POWER: A GROWING CONCERN
Greater DRAM use in portable instruments has designers on a neverending quest for lower-power operation. Currently, designers have two choices: the slow-refresh, low-voltage DRAM, and a new approach called CellularRAM--a memory with an SRAM interface and a pseudostatic DRAM core.
The latter method targets cell phones and other low-power handhelds. The CellularRAM specifications were co-developed by a team consisting of representatives from Cypress Semiconductor Corp., Infineon Technologies, Micron, and Renesas. (For details, go to www.cellularram.com.)
The CelluarRAM pseudostatic memory includes an SRAM and burst NOR flash-compatible interface. It also has a high-bandwidth burst Read and Write capability. Operating from a 1.8-V supply, the memories can perform partial array refresh to minimize active power (40 mA).
The on-chip self-refresh controller includes temperature compensation; thus, the refresh rate will change as the DRAM temperature changes. This ensures the memory cells stay at optimal charge. A deep power-down mode keeps power to a minimum when the CellularRAM isn't being accessed (160 to 250 µA).
Available in densities of 16, 32, 64, and 128 Mbits, the CellularRAM chip layout was designed for multichip packaging and system-in-package applications. Data-transfer rates can run at 66, 80 or 104 MHz, depending on the speed grade.
The alternate approach to the CellularRAM leverages standard DRAM technology, but optimized for low-voltage operation. For instance, Elpida recently released a 256-Mbit super self-refresh (SSR) DDR DRAM that can reduce the refresh current by 95% versus standard DDR memories. Several vendors, including Elpida, Micron, and Samsung, offer Mobile RAM devices in capacities ranging from 64 to 512 Mbits. These memories are based on standard DDR or SDRAM technologies and come in either 16 or 32-bit data widths. Mobile DRAMs based on SDRAM cores are also available from Infineon.
The SSR technology added on-chip error-correction circuitry to check and correct the data when the DRAM exits the self-refresh cycle. On-chip temperature sensors commonly known as auto-temperature compensated self-refresh (ATCSR) are used with the SSR technology to allow the circuity to automatically adjust the self-refresh timing to compensate for internal temperature variations. Thus, self-refresh currents can be trimmed to as little as 40 µA at 25°C and only 150 µA at 70°C.