FCRAM
Another contender for the non-PC DRAM arena is FCRAM. Jointly developed by Fujitsu and Toshiba, FCRAM is a superset of the DDR JEDEC standard. It delivers a 25-ns Read/Write cycle that's about twice as fast as SDRAM (Fig. 2). And, it does it with lower power consumption.
Currently, FCRAM is available in 256-Mbit configurations, with 200- and 154-MHz speed grades. The chips are organized into 16-Mbit by 16-bit or 32-Mbit by 8-bit configurations, each with four on-chip banks. The chips come in a 66-pin, low-cost TSOP (II) package.
Using four of these chips, designers can build a 64-bit wide, 200-MHz memory system with a burst bandwidth of 3.2 Gbytes/s. Wider system buses can up the collective bandwidth. But this bus expansion will need careful design and the use of registered memory modules to minimize skew. FCRAM builds on the standard DRAM core cells.
FCRAM gets fast cycles from a high-speed implementation of the RAS and CAS cycles. The address is latched in 16 bits at a time. The overall access cycles are further reduced with an internal precharge, which does not slow the basic access cycle.
Additionally, FCRAM cuts power by reducing wordline activation power. Only the addressed word is activated. The rest of the words in the line are not. The autoprecharge also is tuned to reduce power. The memory chips use a 2.5-V core voltage to further reduce power consumption. Overall, the FCRAM reduces power dissipation to less than 50% of that of a comparable SDRAM.
A special version of FCRAM has been configured by Fujitsu for mobile phone and portable applications. This memory chip family, the MB82D01171A, provides an SRAM interface and low power dissipation. It's organized as a 16-Mbit by 16-bit memory, with a 90-ns Read cycle time. Maximum currents are limited to 20 mA for active current, 200/100/70 µA for standby, and 10 µA for power-down. The operating voltage is 2.3 to 2.7 V or 2.7 to 3.1 V. The chip comes in a 48-pin plastic FPGA package.
DRAM architectures come and go. What happens to embedded and telecom applications that still need outmoded DRAM parts for deployed products? Not to worry. Integrated Silicon Systems Inc., a fabless memory vendor, has a solution. It builds outmoded DRAM chips on modern fabs, providing pin compatibility with lower power dissipation for chips that currently range from 4- to 64-Mbit DRAMs, as well as SDRAMs.
FCRAM
Another contender for the non-PC DRAM arena is FCRAM. Jointly developed by Fujitsu and Toshiba, FCRAM is a superset of the DDR JEDEC standard. It delivers a 25-ns Read/Write cycle that's about twice as fast as SDRAM (Fig. 2). And, it does it with lower power consumption.
Currently, FCRAM is available in 256-Mbit configurations, with 200- and 154-MHz speed grades. The chips are organized into 16-Mbit by 16-bit or 32-Mbit by 8-bit configurations, each with four on-chip banks. The chips come in a 66-pin, low-cost TSOP (II) package.
Using four of these chips, designers can build a 64-bit wide, 200-MHz memory system with a burst bandwidth of 3.2 Gbytes/s. Wider system buses can up the collective bandwidth. But this bus expansion will need careful design and the use of registered memory modules to minimize skew. FCRAM builds on the standard DRAM core cells.
FCRAM gets fast cycles from a high-speed implementation of the RAS and CAS cycles. The address is latched in 16 bits at a time. The overall access cycles are further reduced with an internal precharge, which does not slow the basic access cycle.
Additionally, FCRAM cuts power by reducing wordline activation power. Only the addressed word is activated. The rest of the words in the line are not. The autoprecharge also is tuned to reduce power. The memory chips use a 2.5-V core voltage to further reduce power consumption. Overall, the FCRAM reduces power dissipation to less than 50% of that of a comparable SDRAM.
A special version of FCRAM has been configured by Fujitsu for mobile phone and portable applications. This memory chip family, the MB82D01171A, provides an SRAM interface and low power dissipation. It's organized as a 16-Mbit by 16-bit memory, with a 90-ns Read cycle time. Maximum currents are limited to 20 mA for active current, 200/100/70 µA for standby, and 10 µA for power-down. The operating voltage is 2.3 to 2.7 V or 2.7 to 3.1 V. The chip comes in a 48-pin plastic FPGA package.
DRAM architectures come and go. What happens to embedded and telecom applications that still need outmoded DRAM parts for deployed products? Not to worry. Integrated Silicon Systems Inc., a fabless memory vendor, has a solution. It builds outmoded DRAM chips on modern fabs, providing pin compatibility with lower power dissipation for chips that currently range from 4- to 64-Mbit DRAMs, as well as SDRAMs.