EDA Alert: June 21, 2005

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
June 21, 2005

=======================================

Today's Table of Contents:
1. Viewpoint Exclusive -- Launching Into The System-To-RTL Continuum
2. OSCI Transfers SystemC 2.1 LRM To The IEEE
3. First Fabless X Architecture Chip Arrives
4. DFM/DFY Tool Addresses 90-nm Designs
5. Industry Gets Behind Composite Current-Source Models
6. Happenings
- International Conference On Mixed Design Of ICs And Systems
(MIXDES 2005)
- International Conference On Engineering Of Reconfigurable
Systems And Algorithms (ERSA 2005)
- Formal Methods And Models For Co-Design (MEMOCODE 2005)
- Globally Asynchronous, Locally Synchronous Design (FMGALS
2005)
- International Symposium On Low-Power Electronics (ISLPED 2005)
- HOT Chips 2005 -- A Symposium On High Performance Chips

************************ ADVERTISEMENT ****************************
This issue sponsored by Mentor Graphics

This week's Top 5 Technical Papers: Are you up-to-date on the latest
technologies?

* Design for Manufacturing: What Designers Need
to Know About the Change in Yield Management
* Bluetooth Transceiver Design with VHDL-AMS
* Challenges of Silicon Modeling in Nanometer Designs
* Bluetooth Transceiver Design: A Top-Down Flow for Complex RF
Mixed-Signal ICs
* Getting Closer to a Top-Down Methodology for RF SoC Design

View all 100+ publications:
http://nls.planetee.com/t?ctl=CA0F:F3222

********************************************************************

TAKE A POLL: What is your personal outlook for design projects in
the next quarter?

-- Concerned about slow down/layoffs
-- Fewer projects, but still feel secure in my position
-- Good stable work flow continues
-- Increased number of projects
-- Lots coming down the pike, maybe more than I can handle

Electronic Design's Quick Poll ==> http://nls.planetee.com/t?ctl=CA02:F3222
*************************************************

Thought you'd missed it? Don't worry; it's archived!
Free Webcast: What to See at DAC

Take a virtual tour of the show floor and get a glimpse of EDA's
premier technology showcase.

Register today at:
http://nls.planetee.com/t?ctl=C9FA:F3222

*************************************************
Get The Lead Out!

The European Union, as well as Japan and China, are about to
restrict the use of environmentally hazardous materials in
electronic components and systems through the Restrictions on
Hazardous Substances (RoHS) directive. Check out Electronic Design's
new RoHS Reference Center with links, articles, and more. Take our
RoHS quiz to see how much you really know about this new EU
directive. Then download the first chapter of our eBook, "Electronic
Design's Guide To New International Environmental Laws." And stay
tuned for more chapters to learn everything you need to know about
this important emerging topic.

RoHS e-book ==> http://nls.planetee.com/t?ctl=CA03:F3222

******************************************************
SUBSCRIBE ONLINE TO ELECTRONIC DESIGN
If you're reading this e-newsletter, then you are either a current
Electronic Design subscriber, or should be (145,000 of your peers
are). To apply for or renew a subscription to Electronic Design
absolutely FREE and without paperwork or hassle, click on
the link below.

Electronic Design subscription ==>
http://nls.planetee.com/t?ctl=CA01:F3222

************
1. Viewpoint -- Exclusive to EDA Alert
************
Launching Into The System-To-RTL Continuum

Devadas Varma, CEO
Calypto Design Systems, Santa Clara, Calif.

In 1961, President John F. Kennedy issued a bold challenge to the
U.S. Congress to put a man on the moon by the end of the decade. At
the time, this challenge seemed virtually impossible. Yet this
vision launched the U.S. space program -- and in less than ten
years, the vision became reality.

Today, the semiconductor industry faces a challenge that may seem as
daunting, and as much of a leap, as putting a man on the moon did in
the 1960s: the challenge of the 100-million-gate chip. These chips
are being designed as part of a system, rather than systems being
designed around several chips. They are, by and large, going into
consumer products with very tight market windows. Typically, their
design descriptions contain millions of lines of code that must be
functionally verified.

Because of these economic and technical factors, design teams are
moving toward higher levels of abstraction, as they did 15 years ago
in the move to RTL. Yet, the gap between system-level and RTL design
has been almost as difficult to traverse as the distance from earth
to the moon in 1961.

The technologies for moving to higher levels of abstraction have not
enabled feasible verification between different levels. Although
behavioral synthesis is available, existing methodologies that
verify resulting RTL are labor-intensive. Likewise, verifying
further refinements to the RTL is so labor-intensive that the design
team often opts not to do them, thus sacrificing RTL quality (and
therefore performance, power consumption, or area). If they choose
to do the verification, they must sacrifice time-to-market. For some
companies, the tradeoff has become worth it. For many others,
though, it's not.

New design methodologies will only be adopted when they improve such
tradeoffs to further optimize, not worsen, time-to-results. As a
result, only a few companies today have made the leap to ESL-based
IC design. Others will do so only when they can verify the results.

To understand how companies will move to ESL-based IC design, we
should look again at the space program. NASA didn't launch a man in
a rocket to the moon the day after President Kennedy's speech.
Rather, they used the fact that space is a single continuum to move
up from earth step by step: First with manned earth-orbital flights,
then with lunar orbital flights. We only made that final leap to a
moon landing after we had already proven and gained the confidence
through staged tests that we had the technology to successfully
accomplish our mission.

Likewise, the EDA industry must approach levels of abstraction
between RTL and the system level as a continuum -- from fully timed,
bit-level descriptions to untimed, transactional models with
word-level abstraction. Also, we must put the right technologies in
place to ease the verification burden of going from system level to
RTL. Only with these technologies in place will we ease the
transition between RTL and higher levels of abstraction. But we must
recognize that most design teams cannot afford a full "leap of
faith" to system level. They will move up through the system-to-RTL
continuum, keeping in touch with their RTL design techniques on the
way.

Contact Devadas Varma at: mailto:dvarma@calypto.com

To comment on this Viewpoint, go to Reader Comments at the foot of
the Web page:
EDA Alert ==>
http://nls.planetee.com/t?ctl=C9FB:F3222

************************************************************
*******
2. News
*******
OSCI Transfers SystemC 2.1 LRM To The IEEE

The Open SystemC Initiative (OSCI) officially transferred the
Language Reference Manual (LRM) for SystemC 2.1 to the IEEE for
further standardization. The LRM, the definitive description of
SystemC 2.1, provides a precise and complete specification of the
SystemC library so that implementations can be developed with
reference to the SystemC standard alone.

The SystemC 2.1 LRM comes after more than a year of intensive
development on the part of the OSCI technical committee. Victor
Berman, chairman of the P1666 Working Group at IEEE, noted that his
technical team worked closely with OSCI during the LRM's development
and that its contents are already incorporated into the draft
standard proposal.

The SystemC 2.1 LRM defines the public interface to the SystemC
class library and defines constraints on how those classes may be
used. It provides an unambiguous definition of what is required to
accurately implement SystemC tools. The SystemC 2.1 LRM is available
at OSCI's Web site.

Open SystemC Initiative ==> http://nls.planetee.com/t?ctl=CA0A:F3222

*******
3. News
*******
First Fabless X Architecture Chip Arrives

The triumvirate of ATI Technologies, Cadence Design Systems, and
TSMC has successfully produced the foundry industry's first X
Architecture device. The ATI chip is a PCI-Express graphics
processor designed for desktop and notebook computers.

The ATI device was implemented using Cadence's design tools, which
enable the pervasive use of diagonal routing, and manufactured using
TSMC's 0.11-micron process. This implementation eliminated one metal
layer from the original Manhattan design, reducing die costs. The
new device is expected to enter volume production late in the year.

To bring the X Architecture into manufacturing reality, TSMC created
extensive test structures to formulate competitive X Architecture
design rules. The company also developed a unique OPC model, as well
as mask-making techniques. Furthermore, enhanced technology files
handle diagonal design rules and parasitic extraction.

ATI Technologies ==> http://nls.planetee.com/t?ctl=CA0E:F3222
Cadence ==> http://nls.planetee.com/t?ctl=CA0B:F3222
TSMC ==> http://nls.planetee.com/t?ctl=CA0D:F3222

*******
4. News
*******
DFM/DFY Tool Addresses 90-nm Designs

With manufacturability and yield issues forcing their consideration
earlier in the design flow, Magma Design Automation is targeting
this need with Blast Yield, a design-for-manufacturability (DFM) and
design-for-yield (DFY) tool for IC designs at 90 nm and below.

Blast Yield features functional cell-yield optimization, where yield
is concurrently optimized with other metrics such as timing, area,
and power for optimum design performance. Yield-aware technology
mapping and cell sizing is used to ensure optimum selection of logic
cells and sizes that will meet timing and produce better yield.

Blast Yield pricing starts at $300,000 per year for a three-year,
time-based license. Full volume shipment is expected to begin at the
end of the year.

Magma Design Automation ==> http://nls.planetee.com/t?ctl=CA07:F3222

*******
5. News
*******
Industry Gets Behind Composite Current-Source Models

ARM, TMSC, Virage Logic, and Library Technologies announced their
intent to include Synopsys' open-source Liberty composite
current-source (CCS) models in their intellectual property (IP) for
semiconductor design. CCS enables high-accuracy delay calculation to
within 2% of Synopsys' HSpice circuit simulator, allowing for higher
design quality in less time with the Synopsys Galaxy Design
Platform.

CCS is a new approach for accurate gate-level delay calculation with
detailed RC parasitics. It provides for efficient representation of
transistor-level driver and receiver characteristics for each
library cell. CCS claims to offer the highest accuracy relative to
circuit simulation, and is designed to provide a unified foundation
model for cell delay, noise, power, and variation. Using CCS
technology, designers can scale back on design margins and produce
higher-performance designs with smaller areas.

Synopsys ==> http://nls.planetee.com/t?ctl=CA06:F3222

**************
6. Happenings
**************
International Conference On Mixed Design Of ICs And Systems (MIXDES
2005)
Hotel Pegaz, Krakow, Poland
June 22-25, 2005
http://nls.planetee.com/t?ctl=CA09:F3222

International Conference On Engineering Of Reconfigurable Systems
And Algorithms (ERSA 2005)
Monte Carlo Resort, Las Vegas, Nev.
June 27-30, 2005
http://nls.planetee.com/t?ctl=C9FF:F3222

Formal Methods And Models For Co-Design (MEMOCODE 2005)
Polo Zanotto, Verona, Italy
July 11-15, 2005
http://nls.planetee.com/t?ctl=C9FD:F3222

Globally Asynchronous, Locally Synchronous Design (FMGALS 2005)
Polo Zanotto, Verona, Italy
July 15, 2005
http://nls.planetee.com/t?ctl=C9FC:F3222

International Symposium On Low-Power Electronics (ISLPED 2005)
Hotel Marriott Del Mar, San Diego, Calif.
August 8-10, 2005
http://nls.planetee.com/t?ctl=CA0C:F3222

HOT Chips 2005 -- A Symposium On High Performance Chips
Stanford University, Palo Alto, Calif.
August 14-16, 2005
http://nls.planetee.com/t?ctl=CA05:F3222

************************************************************
Take the Infineon Memory Challenge

We have an all new pop-quiz for you to test your memory skills on!
Take a whack at the five memory-related questions and you could win
a super-duper Sony Playstation Portable device. We'll also be
throwing a few Electronic Design T-shirts into this month's quiz, so
put your knowledge to the test and hit that submit button!

http://nls.planetee.com/t?ctl=C9FE:F3222
************************************************************
A Closer Look At Video Signals

Nowadays there are numerous standards for the digital video signals
widely used in such products as game players and cell phones. Tough
design questions arise, however, because those digital signals must
be dealt with in an analog domain. Get the answers in a new eBook,
"Analog/Mixed-Signal Components For 21st Century Video," by
Analog/Power Editor Don Tuite.

http://nls.planetee.com/t?ctl=CA00:F3222
*****************************************************************

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

You've received this e-Newsletter for one of three reasons:
1) you received our EDA Alert Newsletter in the past,
2) you've signed up for it at http://nls.planetee.com/t?ctl=CA08:F3222 or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe visit our e-newsletter subscription center at
http://www.planetee.com/Index.cfm?Action=Email

To unsubscribe click here
http://nls.planetee.com/u?id=66786401EB36987562B5BC35A4281E1A

PlanetEE's e-Newsletter homepage:
http://www.planetee.com/Index.cfm?Action=Email

===============================
Copyright 2005 Penton Media Inc.
45 Eisenhower Dr., Paramus, NJ 07652

============================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
June 21, 2005

=======================================

Today's Table of Contents:
1. Viewpoint Exclusive -- Launching Into The System-To-RTL Continuum
2. OSCI Transfers SystemC 2.1 LRM To The IEEE
3. First Fabless X Architecture Chip Arrives
4. DFM/DFY Tool Addresses 90-nm Designs
5. Industry Gets Behind Composite Current-Source Models
6. Happenings
- International Conference On Mixed Design Of ICs And Systems
(MIXDES 2005)
- International Conference On Engineering Of Reconfigurable
Systems And Algorithms (ERSA 2005)
- Formal Methods And Models For Co-Design (MEMOCODE 2005)
- Globally Asynchronous, Locally Synchronous Design (FMGALS
2005)
- International Symposium On Low-Power Electronics (ISLPED 2005)
- HOT Chips 2005 -- A Symposium On High Performance Chips

************************ ADVERTISEMENT ****************************
This issue sponsored by Mentor Graphics

This week's Top 5 Technical Papers: Are you up-to-date on the latest
technologies?

* Design for Manufacturing: What Designers Need
to Know About the Change in Yield Management
* Bluetooth Transceiver Design with VHDL-AMS
* Challenges of Silicon Modeling in Nanometer Designs
* Bluetooth Transceiver Design: A Top-Down Flow for Complex RF
Mixed-Signal ICs
* Getting Closer to a Top-Down Methodology for RF SoC Design

View all 100+ publications:
http://nls.planetee.com/t?ctl=CA0F:F3222

********************************************************************

TAKE A POLL: What is your personal outlook for design projects in
the next quarter?

-- Concerned about slow down/layoffs
-- Fewer projects, but still feel secure in my position
-- Good stable work flow continues
-- Increased number of projects
-- Lots coming down the pike, maybe more than I can handle

Electronic Design's Quick Poll ==> http://nls.planetee.com/t?ctl=CA02:F3222
*************************************************

Thought you'd missed it? Don't worry; it's archived!
Free Webcast: What to See at DAC

Take a virtual tour of the show floor and get a glimpse of EDA's
premier technology showcase.

Register today at:
http://nls.planetee.com/t?ctl=C9FA:F3222

*************************************************
Get The Lead Out!

The European Union, as well as Japan and China, are about to
restrict the use of environmentally hazardous materials in
electronic components and systems through the Restrictions on
Hazardous Substances (RoHS) directive. Check out Electronic Design's
new RoHS Reference Center with links, articles, and more. Take our
RoHS quiz to see how much you really know about this new EU
directive. Then download the first chapter of our eBook, "Electronic
Design's Guide To New International Environmental Laws." And stay
tuned for more chapters to learn everything you need to know about
this important emerging topic.

RoHS e-book ==> http://nls.planetee.com/t?ctl=CA03:F3222

******************************************************
SUBSCRIBE ONLINE TO ELECTRONIC DESIGN
If you're reading this e-newsletter, then you are either a current
Electronic Design subscriber, or should be (145,000 of your peers
are). To apply for or renew a subscription to Electronic Design
absolutely FREE and without paperwork or hassle, click on
the link below.

Electronic Design subscription ==>
http://nls.planetee.com/t?ctl=CA01:F3222

************
1. Viewpoint -- Exclusive to EDA Alert
************
Launching Into The System-To-RTL Continuum

Devadas Varma, CEO
Calypto Design Systems, Santa Clara, Calif.

In 1961, President John F. Kennedy issued a bold challenge to the
U.S. Congress to put a man on the moon by the end of the decade. At
the time, this challenge seemed virtually impossible. Yet this
vision launched the U.S. space program -- and in less than ten
years, the vision became reality.

Today, the semiconductor industry faces a challenge that may seem as
daunting, and as much of a leap, as putting a man on the moon did in
the 1960s: the challenge of the 100-million-gate chip. These chips
are being designed as part of a system, rather than systems being
designed around several chips. They are, by and large, going into
consumer products with very tight market windows. Typically, their
design descriptions contain millions of lines of code that must be
functionally verified.

Because of these economic and technical factors, design teams are
moving toward higher levels of abstraction, as they did 15 years ago
in the move to RTL. Yet, the gap between system-level and RTL design
has been almost as difficult to traverse as the distance from earth
to the moon in 1961.

The technologies for moving to higher levels of abstraction have not
enabled feasible verification between different levels. Although
behavioral synthesis is available, existing methodologies that
verify resulting RTL are labor-intensive. Likewise, verifying
further refinements to the RTL is so labor-intensive that the design
team often opts not to do them, thus sacrificing RTL quality (and
therefore performance, power consumption, or area). If they choose
to do the verification, they must sacrifice time-to-market. For some
companies, the tradeoff has become worth it. For many others,
though, it's not.

New design methodologies will only be adopted when they improve such
tradeoffs to further optimize, not worsen, time-to-results. As a
result, only a few companies today have made the leap to ESL-based
IC design. Others will do so only when they can verify the results.

To understand how companies will move to ESL-based IC design, we
should look again at the space program. NASA didn't launch a man in
a rocket to the moon the day after President Kennedy's speech.
Rather, they used the fact that space is a single continuum to move
up from earth step by step: First with manned earth-orbital flights,
then with lunar orbital flights. We only made that final leap to a
moon landing after we had already proven and gained the confidence
through staged tests that we had the technology to successfully
accomplish our mission.

Likewise, the EDA industry must approach levels of abstraction
between RTL and the system level as a continuum -- from fully timed,
bit-level descriptions to untimed, transactional models with
word-level abstraction. Also, we must put the right technologies in
place to ease the verification burden of going from system level to
RTL. Only with these technologies in place will we ease the
transition between RTL and higher levels of abstraction. But we must
recognize that most design teams cannot afford a full "leap of
faith" to system level. They will move up through the system-to-RTL
continuum, keeping in touch with their RTL design techniques on the
way.

Contact Devadas Varma at: mailto:dvarma@calypto.com

To comment on this Viewpoint, go to Reader Comments at the foot of
the Web page:
EDA Alert ==>
http://nls.planetee.com/t?ctl=C9FB:F3222

************************************************************
*******
2. News
*******
OSCI Transfers SystemC 2.1 LRM To The IEEE

The Open SystemC Initiative (OSCI) officially transferred the
Language Reference Manual (LRM) for SystemC 2.1 to the IEEE for
further standardization. The LRM, the definitive description of
SystemC 2.1, provides a precise and complete specification of the
SystemC library so that implementations can be developed with
reference to the SystemC standard alone.

The SystemC 2.1 LRM comes after more than a year of intensive
development on the part of the OSCI technical committee. Victor
Berman, chairman of the P1666 Working Group at IEEE, noted that his
technical team worked closely with OSCI during the LRM's development
and that its contents are already incorporated into the draft
standard proposal.

The SystemC 2.1 LRM defines the public interface to the SystemC
class library and defines constraints on how those classes may be
used. It provides an unambiguous definition of what is required to
accurately implement SystemC tools. The SystemC 2.1 LRM is available
at OSCI's Web site.

Open SystemC Initiative ==> http://nls.planetee.com/t?ctl=CA0A:F3222

*******
3. News
*******
First Fabless X Architecture Chip Arrives

The triumvirate of ATI Technologies, Cadence Design Systems, and
TSMC has successfully produced the foundry industry's first X
Architecture device. The ATI chip is a PCI-Express graphics
processor designed for desktop and notebook computers.

The ATI device was implemented using Cadence's design tools, which
enable the pervasive use of diagonal routing, and manufactured using
TSMC's 0.11-micron process. This implementation eliminated one metal
layer from the original Manhattan design, reducing die costs. The
new device is expected to enter volume production late in the year.

To bring the X Architecture into manufacturing reality, TSMC created
extensive test structures to formulate competitive X Architecture
design rules. The company also developed a unique OPC model, as well
as mask-making techniques. Furthermore, enhanced technology files
handle diagonal design rules and parasitic extraction.

ATI Technologies ==> http://nls.planetee.com/t?ctl=CA0E:F3222
Cadence ==> http://nls.planetee.com/t?ctl=CA0B:F3222
TSMC ==> http://nls.planetee.com/t?ctl=CA0D:F3222

*******
4. News
*******
DFM/DFY Tool Addresses 90-nm Designs

With manufacturability and yield issues forcing their consideration
earlier in the design flow, Magma Design Automation is targeting
this need with Blast Yield, a design-for-manufacturability (DFM) and
design-for-yield (DFY) tool for IC designs at 90 nm and below.

Blast Yield features functional cell-yield optimization, where yield
is concurrently optimized with other metrics such as timing, area,
and power for optimum design performance. Yield-aware technology
mapping and cell sizing is used to ensure optimum selection of logic
cells and sizes that will meet timing and produce better yield.

Blast Yield pricing starts at $300,000 per year for a three-year,
time-based license. Full volume shipment is expected to begin at the
end of the year.

Magma Design Automation ==> http://nls.planetee.com/t?ctl=CA07:F3222

*******
5. News
*******
Industry Gets Behind Composite Current-Source Models

ARM, TMSC, Virage Logic, and Library Technologies announced their
intent to include Synopsys' open-source Liberty composite
current-source (CCS) models in their intellectual property (IP) for
semiconductor design. CCS enables high-accuracy delay calculation to
within 2% of Synopsys' HSpice circuit simulator, allowing for higher
design quality in less time with the Synopsys Galaxy Design
Platform.

CCS is a new approach for accurate gate-level delay calculation with
detailed RC parasitics. It provides for efficient representation of
transistor-level driver and receiver characteristics for each
library cell. CCS claims to offer the highest accuracy relative to
circuit simulation, and is designed to provide a unified foundation
model for cell delay, noise, power, and variation. Using CCS
technology, designers can scale back on design margins and produce
higher-performance designs with smaller areas.

Synopsys ==> http://nls.planetee.com/t?ctl=CA06:F3222

**************
6. Happenings
**************
International Conference On Mixed Design Of ICs And Systems (MIXDES
2005)
Hotel Pegaz, Krakow, Poland
June 22-25, 2005
http://nls.planetee.com/t?ctl=CA09:F3222

International Conference On Engineering Of Reconfigurable Systems
And Algorithms (ERSA 2005)
Monte Carlo Resort, Las Vegas, Nev.
June 27-30, 2005
http://nls.planetee.com/t?ctl=C9FF:F3222

Formal Methods And Models For Co-Design (MEMOCODE 2005)
Polo Zanotto, Verona, Italy
July 11-15, 2005
http://nls.planetee.com/t?ctl=C9FD:F3222

Globally Asynchronous, Locally Synchronous Design (FMGALS 2005)
Polo Zanotto, Verona, Italy
July 15, 2005
http://nls.planetee.com/t?ctl=C9FC:F3222

International Symposium On Low-Power Electronics (ISLPED 2005)
Hotel Marriott Del Mar, San Diego, Calif.
August 8-10, 2005
http://nls.planetee.com/t?ctl=CA0C:F3222

HOT Chips 2005 -- A Symposium On High Performance Chips
Stanford University, Palo Alto, Calif.
August 14-16, 2005
http://nls.planetee.com/t?ctl=CA05:F3222

************************************************************
Take the Infineon Memory Challenge

We have an all new pop-quiz for you to test your memory skills on!
Take a whack at the five memory-related questions and you could win
a super-duper Sony Playstation Portable device. We'll also be
throwing a few Electronic Design T-shirts into this month's quiz, so
put your knowledge to the test and hit that submit button!

http://nls.planetee.com/t?ctl=C9FE:F3222
************************************************************
A Closer Look At Video Signals

Nowadays there are numerous standards for the digital video signals
widely used in such products as game players and cell phones. Tough
design questions arise, however, because those digital signals must
be dealt with in an analog domain. Get the answers in a new eBook,
"Analog/Mixed-Signal Components For 21st Century Video," by
Analog/Power Editor Don Tuite.

http://nls.planetee.com/t?ctl=CA00:F3222
*****************************************************************

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

You've received this e-Newsletter for one of three reasons:
1) you received our EDA Alert Newsletter in the past,
2) you've signed up for it at http://nls.planetee.com/t?ctl=CA08:F3222 or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

To subscribe visit our e-newsletter subscription center at
http://www.planetee.com/Index.cfm?Action=Email

To unsubscribe click here
http://nls.planetee.com/u?id=66786401EB36987562B5BC35A4281E1A

PlanetEE's e-Newsletter homepage:
http://www.planetee.com/Index.cfm?Action=Email

===============================
Copyright 2005 Penton Media Inc.
45 Eisenhower Dr., Paramus, NJ 07652