Cygnal Integrated Products also gives its 25-MHz flash memory a boost of four times, enabling the 8051 processor core to run at 100 MHz. The company uses a 32-bit wide flash memory to supply the 8-bit instruction stream to the processor, but this is only a start. A 4-byte prefetch buffer provides sufficient buffering to allow sequential access to the flash memory at the 100-MHz rate.
Moreover, Cygnal includes a 64-entry instruction cache to keep things moving when the application execution varies from a sequential flow. The 32-bit entries feed the prefetch buffer, allowing the processor to run at full speed as long as code is accessed sequentially, or the code is contained in the instruction cache.
Ubicom's 120-MIPS (millions of instructions/s) IP2202 needs to run at top speed in many communications environments, which is why it packs two banks of SRAM. One bank can be used for program memory if an application explicitly moves code from flash memory to SRAM. Applications can run directly from flash memory, but only with corresponding hits in performance and power. The trick for programmers is to keep frequently executed code in SRAM. This isn't too difficult given the availability of 16 kbytes of SRAM for the task. The split between code and data in this SRAM was arbitrarily decided upon to allow developers to trade off faster execution speed for more data space.
Making It Secure: While lower power and high speed are the usual considerations associated with flash-based microcontroller designs, security is an often overlooked feature. A number of different security issues come into play with flash microcontrollers. Protecting the code from snoopers is a concern to many whose intellectual property is frequently the main distinguishing factor in many products based on flash microcontrollers. Another issue is the prevention of improper read or write accesses. Restriction of read access enables data to be hidden or encrypted while the prevention of accidental writes protects an application from overwriting itself.
With regard to securing application code, Eugene Feng, business director of application specific product group for Silicon Storage Technology (SST), says that flash memory is more sensitive to physical dissection than ROM. So while a determined pirate could crack open a chip and access a ROM directly, accessing a flash memory in this way will usually corrupt its contents.
SST's FlashFlex51 family of 8051-compatible microcontrollers uses the company's SuperFlash CMOS technology. Its SoftLock feature prevents flash memory updates. The feature is en-abled by setting an address in flash memory for the routine allowed to perform the updates. Knowing the address for this routine, how it works, and where it's located will be necessary to update the flash memory.
SST's secure programming takes advantage of SST's in-application programming (IAP). IAP has a deterministic write time and can employ a dual- block configuration, which allows writes to occur in one block while another block accesses program code.
Switching blocks could be a problem for interrupts that implement an interrupt vector in flash memory. SST addresses this possibility by allowing interrupts to be redirected to a different flash-memory block.
Because SST's sector size is just 64 bytes, it requires fine-grain control. But the small sector size also eliminates the need to update much larger blocks (64 kbytes for many other systems).
Another feature of the SuperFlash technology, soft partition support, lets data be stored in flash memory that's not used for program memory. A DMA engine and mailbox register interface enables the use of flash memory as data storage without significantly affecting program execution. The interface moves data in the background instead of requiring an application to wait for the completion of flash memory writes.
Whatever the embedded-system design needs—low power, high performance, or security—flash memory technologies exist to deliver the features. As a result, flash memory-based microcontrollers will be the primary choice for embedded-system designs for many years to come.
Cygnal Integrated Products also gives its 25-MHz flash memory a boost of four times, enabling the 8051 processor core to run at 100 MHz. The company uses a 32-bit wide flash memory to supply the 8-bit instruction stream to the processor, but this is only a start. A 4-byte prefetch buffer provides sufficient buffering to allow sequential access to the flash memory at the 100-MHz rate.
Moreover, Cygnal includes a 64-entry instruction cache to keep things moving when the application execution varies from a sequential flow. The 32-bit entries feed the prefetch buffer, allowing the processor to run at full speed as long as code is accessed sequentially, or the code is contained in the instruction cache.
Ubicom's 120-MIPS (millions of instructions/s) IP2202 needs to run at top speed in many communications environments, which is why it packs two banks of SRAM. One bank can be used for program memory if an application explicitly moves code from flash memory to SRAM. Applications can run directly from flash memory, but only with corresponding hits in performance and power. The trick for programmers is to keep frequently executed code in SRAM. This isn't too difficult given the availability of 16 kbytes of SRAM for the task. The split between code and data in this SRAM was arbitrarily decided upon to allow developers to trade off faster execution speed for more data space.
Making It Secure: While lower power and high speed are the usual considerations associated with flash-based microcontroller designs, security is an often overlooked feature. A number of different security issues come into play with flash microcontrollers. Protecting the code from snoopers is a concern to many whose intellectual property is frequently the main distinguishing factor in many products based on flash microcontrollers. Another issue is the prevention of improper read or write accesses. Restriction of read access enables data to be hidden or encrypted while the prevention of accidental writes protects an application from overwriting itself.
With regard to securing application code, Eugene Feng, business director of application specific product group for Silicon Storage Technology (SST), says that flash memory is more sensitive to physical dissection than ROM. So while a determined pirate could crack open a chip and access a ROM directly, accessing a flash memory in this way will usually corrupt its contents.
SST's FlashFlex51 family of 8051-compatible microcontrollers uses the company's SuperFlash CMOS technology. Its SoftLock feature prevents flash memory updates. The feature is en-abled by setting an address in flash memory for the routine allowed to perform the updates. Knowing the address for this routine, how it works, and where it's located will be necessary to update the flash memory.
SST's secure programming takes advantage of SST's in-application programming (IAP). IAP has a deterministic write time and can employ a dual- block configuration, which allows writes to occur in one block while another block accesses program code.
Switching blocks could be a problem for interrupts that implement an interrupt vector in flash memory. SST addresses this possibility by allowing interrupts to be redirected to a different flash-memory block.
Because SST's sector size is just 64 bytes, it requires fine-grain control. But the small sector size also eliminates the need to update much larger blocks (64 kbytes for many other systems).
Another feature of the SuperFlash technology, soft partition support, lets data be stored in flash memory that's not used for program memory. A DMA engine and mailbox register interface enables the use of flash memory as data storage without significantly affecting program execution. The interface moves data in the background instead of requiring an application to wait for the completion of flash memory writes.
Whatever the embedded-system design needs—low power, high performance, or security—flash memory technologies exist to deliver the features. As a result, flash memory-based microcontrollers will be the primary choice for embedded-system designs for many years to come.