Magnetoresistive memory (MRAM) substitutes a magnetic material for the DRAM storage capacitor and flash dielectric to hold a programmed value. Because the material can hold its state, MRAM is a nonvolatile memory. Unlike FRAM, its Reads aren't destructive. Therefore, it doesn't require a restorative Write after a Read. Moreover, its Writes and Reads are symmetric with a 50-ns Read and Write. It also has no endurance limitations. Memory retention is on the order of a satisfactory 10 years. MRAM implementations can be done with supply voltages in the 2.5- to 3.3-V range. They can be run at a lower 1.8 V, however, which makes them attractive for low-power, nonvolatile consumer applications.
MRAM has a way to go before be-coming a mainstream technology. One problem may be material compatibility in integrating the magnetic material into a silicon process for reliable production. Additionally, MRAM requires a high Write current of up to 10 mA. That may be a problem for low-power operation, limiting Write widths to minimize the overall Write current. It means that programming MRAM may be a long-time affair. Plus, it takes a fairly large cell to build MRAM. For instance, Motorola's MRAM uses a metal junction transistor for each bit, but it also uses a transistor switch on each bit line and word line.
A number of vendors are working on MRAM. Motorola announced a 256-kbit CMOS chip fabricated using 0.6-µm design rules at this year's International Solid State Circuits Conference. The MRAM offered 35-ns Read and Write times (Fig. 4). The company expects to have 32-Mbit or larger MRAMs in production by 2004. Also, IBM has partnered with Infineon in an MRAM development effort.
Arthur Koestler defined creativity as bi-association, the bringing together of two separate things to create a new integrated whole. OUM does that. It combines silicon memory technology with the storage medium used for re-writable CDs and DVDs—chalcogenide material alloys (Fig. 5).
Chalcogenide, a metal alloy (Ge-SbTe), is used as the storage medium. The metal can take on crystalline conductive or amporhous nonconductive phases, which are conductive or resistive, respectively. State can then be stored by turning the bit material into a conductor or a resistor, a state that is detectable by measuring the bit cell's resistance. The bit state is changed by heating a small amount of the chalcogenide material using an electric current. When the material melts, it loses all crystalline structure and becomes a resistor.
This is a nonvolatile memory. Reads are nondestructive. The cell technology can run at low voltage, and it doesn't dissipate much power. It also supports 1012 Write/erase cycles. Write speed is on the order of 100 ns, which is good enough for many nonvolatile code-storage applications.
Ovonyx, working with Intel, has fabricated a 1-Mbit OUM test chip, built using 0.18-µm lithography. Intel has projected that the technology will easily scale down to 0.10 µm and lower and is working to achieve this. Other vendors working with OUM include STMicroelectronics and British Aerospace. The aerospace industry has demonstrated an interest in OUM for high-reliability, nonvolatile memory applications with a number of research projects exploring the memory technology.
Polymer Memory
Polymer memory builds on a polymeric ferroelectric material. This consists of a polymer material made up of polymer chains with a dipole moment. The dipole is used to store data by changing the polarization of the polymer. The polymer material is sandwiched between two metal lines, which expose the material to a measured voltage. This arrangement eliminates the 1T storage cell, as there are no transistors per cell. Moreover, these polymer layers can be stacked with a polymer layer between different bit layers (Fig. 6).
The individual polymer addressed bits are activated by word and bit lines. A common set of sense amplifiers in the CMOS base wafer sense the memory bit values. Reads and Writes are on the order of 50 µs.
Polymer memory can provide a very low cost per bit with a high chip capacity. The process is simple and can be easily integrated with standard CMOS processes. It uses a small cell size (4 λ2) and can stack up to eight layers for a high chip bit density. The cells don't require any standby power or any refresh cycles, but polymer memory isn't a fast access memory. Cell Read and Write times are on the order of 50 µs, which is adequate for disk-storage applications.
The polymer thin-film memory technology was developed by Thin Film Electronics. The company is owned by Opticom AS, with Intel holding a 6% interest. Thin Film Electronics offers nonexclusive licenses of its technology. Intel is helping to develop the technology, with an option to license the resultant technology. Intel's research is aimed at developing nonvolatile memory products.
Magnetoresistive memory (MRAM) substitutes a magnetic material for the DRAM storage capacitor and flash dielectric to hold a programmed value. Because the material can hold its state, MRAM is a nonvolatile memory. Unlike FRAM, its Reads aren't destructive. Therefore, it doesn't require a restorative Write after a Read. Moreover, its Writes and Reads are symmetric with a 50-ns Read and Write. It also has no endurance limitations. Memory retention is on the order of a satisfactory 10 years. MRAM implementations can be done with supply voltages in the 2.5- to 3.3-V range. They can be run at a lower 1.8 V, however, which makes them attractive for low-power, nonvolatile consumer applications.
MRAM has a way to go before be-coming a mainstream technology. One problem may be material compatibility in integrating the magnetic material into a silicon process for reliable production. Additionally, MRAM requires a high Write current of up to 10 mA. That may be a problem for low-power operation, limiting Write widths to minimize the overall Write current. It means that programming MRAM may be a long-time affair. Plus, it takes a fairly large cell to build MRAM. For instance, Motorola's MRAM uses a metal junction transistor for each bit, but it also uses a transistor switch on each bit line and word line.
A number of vendors are working on MRAM. Motorola announced a 256-kbit CMOS chip fabricated using 0.6-µm design rules at this year's International Solid State Circuits Conference. The MRAM offered 35-ns Read and Write times (Fig. 4). The company expects to have 32-Mbit or larger MRAMs in production by 2004. Also, IBM has partnered with Infineon in an MRAM development effort.
Arthur Koestler defined creativity as bi-association, the bringing together of two separate things to create a new integrated whole. OUM does that. It combines silicon memory technology with the storage medium used for re-writable CDs and DVDs—chalcogenide material alloys (Fig. 5).
Chalcogenide, a metal alloy (Ge-SbTe), is used as the storage medium. The metal can take on crystalline conductive or amporhous nonconductive phases, which are conductive or resistive, respectively. State can then be stored by turning the bit material into a conductor or a resistor, a state that is detectable by measuring the bit cell's resistance. The bit state is changed by heating a small amount of the chalcogenide material using an electric current. When the material melts, it loses all crystalline structure and becomes a resistor.
This is a nonvolatile memory. Reads are nondestructive. The cell technology can run at low voltage, and it doesn't dissipate much power. It also supports 1012 Write/erase cycles. Write speed is on the order of 100 ns, which is good enough for many nonvolatile code-storage applications.
Ovonyx, working with Intel, has fabricated a 1-Mbit OUM test chip, built using 0.18-µm lithography. Intel has projected that the technology will easily scale down to 0.10 µm and lower and is working to achieve this. Other vendors working with OUM include STMicroelectronics and British Aerospace. The aerospace industry has demonstrated an interest in OUM for high-reliability, nonvolatile memory applications with a number of research projects exploring the memory technology.
Polymer Memory
Polymer memory builds on a polymeric ferroelectric material. This consists of a polymer material made up of polymer chains with a dipole moment. The dipole is used to store data by changing the polarization of the polymer. The polymer material is sandwiched between two metal lines, which expose the material to a measured voltage. This arrangement eliminates the 1T storage cell, as there are no transistors per cell. Moreover, these polymer layers can be stacked with a polymer layer between different bit layers (Fig. 6).
The individual polymer addressed bits are activated by word and bit lines. A common set of sense amplifiers in the CMOS base wafer sense the memory bit values. Reads and Writes are on the order of 50 µs.
Polymer memory can provide a very low cost per bit with a high chip capacity. The process is simple and can be easily integrated with standard CMOS processes. It uses a small cell size (4 λ2) and can stack up to eight layers for a high chip bit density. The cells don't require any standby power or any refresh cycles, but polymer memory isn't a fast access memory. Cell Read and Write times are on the order of 50 µs, which is adequate for disk-storage applications.
The polymer thin-film memory technology was developed by Thin Film Electronics. The company is owned by Opticom AS, with Intel holding a 6% interest. Thin Film Electronics offers nonexclusive licenses of its technology. Intel is helping to develop the technology, with an option to license the resultant technology. Intel's research is aimed at developing nonvolatile memory products.