Data-transfer rates are continually increasing, carrying more data from node to node within a network, or from point to point within a system. As a result, generic field-programmable logic arrays cannot meet the performance demanded by high-speed serial data interfaces.
Standalone serializer/deserializer (SERDES) chips can provide the interface between the multigigabit serial channels and the parallel digital logic. Yet these circuits consume extra board space and power while offering a fixed-function solution. With all of the evolving networking, telecommunications, and data communications standards, designers would opt for a more flexible solution. They would prefer to "tune" the interface at the last possible point, just prior to shipping products.
To meet such demanding requirements, QuickLogic has combined the high-speed programmable-logic architecture of its recently released Eclipse FPGA family with dedicated, on-chip, configurable SERDES blocks. The result of this work is the QuickSD family of antifuse-based FPGAs, which the company refers to as embedded-system platforms (ESPs).
There will be three chips in the initial family, the QL81SD, 82SD, and 84SD. The QL81SD has six SERDES channels and 334k system gates, while the QL82SD has eight SERDES ports and 536 kgates. Available with the QL84SD are eight SERDES ports and 658 kgates. Each SERDES port can operate at data speeds of up to 1 Gbit/s and is OC-12 (622 MHz) compatible for use in SONET applications.
In addition to the high-speed serial ports, the QuickSD chips come with two programmable SERDES clock circuits that can provide high-speed clocks if timing information is not embedded in the data. Also included on the chips are two high-speed programmable PLLs, 24 to 36 blocks (2304 bits/block) of dual-ported SRAM, and 12 to 18 quad-port multiplier-accumulator (QMAC) blocks (Fig. 1). The QMAC blocks are part of the intellectual property QuickLogic developed for its QuickDSP FPGA family. They can greatly accelerate DSP-type computations such as those found in wireless basestations and many other applications.
The resulting aggregate bandwidth on the SERDES interfaces totals 8 Gbits/s. Such high-performance, flexible circuitry can readily tackle the data movement and processing needs of systems performing data transmission, image processing, and other tasks. It can even form the heart of a virtual backplane or crosspoint switch to replace wide, high-speed buses.
To achieve high data rates with minimal noise, the fast, custom-designed serial interfaces employ low-voltage differential signaling. The LVDS interfaces on the SERDES ports can actually reach data rates well in excess of the 622 Mbits/s specified by the OC-12 standard.
At top speed, the LVDS I/O pins can operate at 1 Gbit/s, which pushes the overall total data throughput far above 8 Gbits/s. To keep pace with the recovered/transmitted data, the on-chip memory blocks have to be fast. They're specified for operation at access rates of up to 300 MHz.
In a typical system handling multiple data communications channels, the SERDES blocks would talk to the high-speed data channels. As part of the interface between the SERDES blocks and the programmable logic, the dual-ported RAM can be configured to appear as multiple asynchronous FIFO buffers. On the other side of the buffers, the FPGA logic would be used to perform functions such as encoding, decoding, dc balancing, ATM/SDH packet framing, and memory control. It could even be used to implement an interface—PCI, Utopia, 10/100 Ethernet, or a proprietary control/interface block (Fig. 2).
Each SERDES block provides transceiver logic as well as parallel-to-serial and serial-to-parallel conversion logic. (Fig. 3). Also included with SERDES is a programmable timing-and-control block along with a PLL to recover incoming clocks and precisely control the clock timing. Test circuits, in the form of JTAG, built-in self-test, and a loopback capability, allow designers to check out the circuit functions before, during, and after all the circuits have been configured.
The SERDES blocks can operate with the included clock and data circuitry to recover clock signals embedded in the data stream, or with a separately transmitted clock. This aids in producing very stable and wide timing margins. Consequently, it's easier for the designer to build the rest of the system. Also included is pre-emphasis equalization and dc balancing to help optimize the interface performance.
With dc balancing, the SERDES helps compensate for positive charge buildup on the data channel when long strings of "1s" are sent. The balancing scheme changes the data polarity so that a long string of "1s" will actually look like a short string of "1s" followed by a similar-sized string of "0s." Another string of "1s" follows and so on, until something breaks the long string of "1s." This breaks up the dc charge buildup caused when only "1s" are sent. And, that eliminates the chance that a single-bit "0" in a long string of "1s" will go undetected. Without balancing, the single-bit "0" may not be able to drop the accumulated charge below the level that the detector will recognize as a zero.
The LVDS interface can be used in point-to-point, multipoint, and multidrop bus configurations. That enables the system designer to employ the bus configuration that best matches the system. The LVDS bus interface on the FPGAs allows for an embedded clock in the data—a single "1" start bit and a single "0" stop bit for one byte of data. Moreover, the circuitry can lock into the data stream within 1024 cycles.