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FPGA Design Issues 201
You may be familiar with the basics. But to resolve the challenges that plague today's FPGAs, you need to sign up for the next-level course.
Date Posted: March 15, 2007 12:00 AM
DIFFERENTIAL SIGNALS
You
probably won't find more controversy in FPGA design than in the handling of differential signals. As with
SSN, it's best to absorb as much information from the FPGA vendors,
books, and user groups as possible.
Also, consult your layout house to see
what it recommends before committing to a specific scheme.
Great debates are being waged over
whether differential pairs should be
broadside or edge coupled, and exactly how much coupling should exist
between the pair. The answer is usually some form of "well, it depends," so
research is in order.
If you're unsure why you would
want to choose a differential I/O standard over a single-ended one when
given a choice, the answer is simple.
With differential signals, you have
almost complete control over the signal's return path. That's because it's
part of the pair and, in theory, no current from the pair should appear on
any of the ground (or power) planes.
This is assuming traces are of equal
length, routed in close and constant
proximity, constant and matched
trace impedances, and so on. Also,
with single-ended signals, you have
very little control over the return
path, and debugging a signal's return
can be an exercise in futility.
The major disadvantage of differential signals is that they require two
traces routed in close proximity to
one another. This can be a headache
when routing several hundred of
them on a PCB. But that's the layout
engineer's problem, right?
References
1. Altera Corporation Application
Note 315: Guidelines for Designing
High-Speed FPGA PCBs, published
February 2004
2. Actel Corporation Application
Note: Simultaneous Switching Noise
and Signal Integrity, published June
2006
For The Best FPGA Advice,
Ask The Experts
To prepare for this article, we talked with experts at Actel,
Altera, Lattice Semiconductor,
and Xilinx. We asked them a
series of key design questions,
including:
- What are the top issues your
applications engineers face
on an ongoing basis?
- What flow do you suggest your
customers follow in starting a
new FPGA design?
- What do you suggest to your
customers for handling I/O
signal assignments?
- How do you tell your customers to prepare for a migration path to another FPGA, a structured ASIC, or an ASIC?
Other questions tackled global
and local/regional clocking, the
combination of IP blocks, timing,
and working with EDA companies. To see the full answers to
these questions, check out
"FPGA Q&A: Actel"; "FPGA Q&A: Altera"; "FPGA Q&A:
Lattice Semiconductor"; and "FPGA Q&A:
XIlinx".
Also, see "Top Application Engineering Issues," which compares
their answers in tabular format. |