Electronic Design held a series of Q&A sessions with several major FPGA companies. Here, our roundtable discussion with Xilinx included Frederic Rivoallon, synthesis methodology manager; Philippe Garrault, senior technical marketing engineer; Chris Stinson, senior manager, Product Applications Engineering; Mike Frasier, director of engineering, IP Solutions; Mark Goosman, product marketing manager, Programmable Digital Systems; and Steve Sharp, senior manager, Competitive Programs.
Question: What are the top five to 10 issues your applications engineers deal with on an ongoing basis? How are the problems handled at the customer level, and how are they addressed by the company as a whole?
Answer: If we look at the technical-support case data, some of the top challenges for customers include:
Configuration: This accounts for about 16% of inquiries. We are actively listening to our customers and incorporating their feedback, questions, and issues into the tools and documentation. We are also expanding our Web content to enable customers to quickly find information they need.
Embedded design: This accounts for about 13% of inquiries. Close partnership between applications and development enable quick identification and resolution of issues, as well as driving customer feedback into future requirements and releases.
The top issues relating to the ISE design tools are related to mapping, place-and-route, Project Navigator, and the XST Xilinx Synthesis tool.
Additional areas challenging our customers include memory interfaces, IP integration, and power management.
In addition to providing a domain-optimized silicon platform, Xilinx has taken a solutions-optimized approach to its product portfolio. We offer a comprehensive array of application- and market-specific libraries of reference designs, kits, IP, and software tools designed to shorten development cycles and reduce time-to-market.
Question: What flow do you suggest your customers follow when starting a new FPGA design?
Answer: Customers can use third-party tools, such as XST, Precision, or Synplify, for synthesis, and then use Xilinx ISE 9.1i for place and route. For simulation, customers can use either ModelSim, NC Sim, or VCS. They should always enter timing constraints for synthesis.
Question: What is normally suggested to your customers regarding the handling I/O signal assignments? In what order do you suggest the various signals types be assigned? (That is, start with VREF, move to high-speed I/O, and so on.)
Answer: FPGA I/O assignment must reconcile several times, sometimes contradicting constraints:
- Constraints from the PCB, such as escape routes, board space, and congestion; and signal-integrity effects (length match, max attenuation, max via, etc.)
- Constraints from the FPGA architecture (I/O baking rules, SSO, clocking rules, etc.)
- Constraints from the customer design (timing, location of the logic source/destination within the device, etc.)
Each FPGA architecture/customer design combination will have its own constraints environment. Giving general rules is no easy task. Typically, you first want to loc FPGA pins that have the tightest constraints. A typical order for pin assignment might be:
- Input global/regional clocks, FPGA configuration pins
- MGT (SERDES), high-speed single-ended (memory/CPU interface), differential signals, reserve multipurpose pins that cannot be used as user I/O because of the particular customer design (DCI reference voltages, input reference voltage)
- Other sets of pins (buses) that require grouping into adjacent package pins on the FPGA for internal timing or pc-board (PCB) layout
- Finally, slow signals (reset, etc.)
I/O assignment can be done in multiple ways—ISE (PACE, Floorplan Editor), third-party vendors (Mentor I/O Designer), PlanAhead or even Excel spreadsheet.
Useful resources would be: