When choosing a core, devlopers must consider whether a legacy
architecture is a requirement. One reason for the vendor-specific
cores such as Altera’s Nios II and Xilinx’s MicroBlaze is that
the vendors designed the architectures to take advantage of their
FPGA’s characteristics.
In the past, choosing a legacy architecture often meant that
tools, operating systems, and experienced developers would be
more readily available. These days, vendor cores have been around
long enough to have all of these. In addition, standard development
platforms like Eclipse means software developers will
already be familiar with the tools.
Another tradeoff to consider is on-chip and off-chip memory.
In many instances, memory will be dictated by the application,
such as when there’s a need for large amounts of off-chip memory.
Often enough, though, a single-chip FPGA solution is viable
and comparable to a single-chip microcontroller solution. In
fact, given the FPGA’s flexibility, a single-chip FPGA solution
is typically better than using a microcontroller that will require
additional support chips.
No MMU is required for uCLinux. In fact, it’s often used with
FPGA soft cores that lack MMU support. The more general availability
of MMU support with cores such as Xilinx’s MicroBlaze,
ARM’s Cortex-M1, and LEON3 allow full-blown Linux to be supported,
as well as a range of other higher-end operating systems.
BETTER DEBUGGING
Going with one or more FPGA soft cores can have other development
advantages over a standard microcontroller-based solution.
This is true in debugging because FPGAs can be programmed
with additional debugging hooks that are able to be removed for production units. Therefore, use of a
smaller, less costly FPGA is possible, too.
Most soft cores can be equipped with
the standard breakpoint hooks and even
instruction trace facilities. Other features
include logic analyzer-style trace support
for other soft components within the
FPGA, which can often be synchronized
with instruction trace. Computex provides
trace probes for Xilinx’s MicroBlaze, as
well as logic-analyzer-style support.
Another neat trick offered by some
FPGAs is the ability to read the status of
almost any register in the system without
the need for additional trace support
within the FPGA fabric. Xilinx FPGAs
allow the JTAG port to read while the
device is running.
Almost a third of all hard-core and
soft-core FPGA designs incorporate multiple
cores. Standard interprocessor communication
IP is often available from the
vendors, and it’s usable in operating systems
and applications. For example, Xilinx
features shared or dual-ported memory
and hardware semaphores.
Shared memory is more common than
SMP configurations due to its simplicity.
Most tools automatically generate
the source files to support the interfaces,
such as hardware semaphores, but not any
higher-level communication facilities.
If your custom IP isn’t too complex and
you’re looking for an 8-bit core, consider
Cypress Semiconductor’s PSoC. It can
handle a wide range of chores and includes
mixed-signal support (see “Mixed-Signal
Processors Can Aid Visual Robotic Development,”
ED Online 18513). The PSoC isn’t
as flexible as an FPGA, but its customization
greatly exceeds that of a standard
microcontroller.
Developers use PSoC Designer to configure
the digital and analog interfaces. It’s
similar in functionality to most FPGA tools
like Xilinx’s ISE, but much simpler and easier
to use. The PSoC Express development
tool, which employs a graphical programming
language, is even easier to use.
An FPGA may not fit all design requirements.
Still, developers may discover that it
can be a desirable alternative to standard
microcontrollers.