To DSP Or Not To DSP
FPGAs will
encroach further into DSP territory by dangling a very tantalizing carrot in front of
engineers (especially those dealing with
multiple channels of high-speed data):
hundreds of fixed-point multiplications per
clock cycle that pop out several times
faster than the fastest DSP (comparing
pure hardware to pure software implementations). This makes some applications
once handled by DSP farms ideally suited
for the latest FPGA offerings.
The main issue going forward for FPGA
vendors is to offer a tool set that translates
algorithms into efficient hardware implementations, helping bridge the gap
between complex functionality. The underlying issue involves taking a complex algorithm created in hours or days using MatLab and translating it into a hardware
implementation utilizing an HDL like Verilog or SystemC.
Often, the end result takes an order of
magnitude longer to reproduce and tweak
the same algorithm using an HDL, and
implementation will look nothing like an
algorithm and instead come out as a jumbled mess. Yet the prospect of handling several channels of data using a single
FPGA, with room left over for a general-purpose processor and other functional
blocks, may be enough to overcome the
design time woes. In some cases, an FPGA
or massively parallel processor may be the
only way to go.
"Where parallelism is important,
FPGAs are better than DSP processors,"
says Altera's Biran. "Processors have hit
a wall in what they can get from process
improvement, leading processor companies to move toward dual-core and multicore implementations. FPGAs are inherently built of many processing elements
that can operate in parallel, which is
what the processing platforms of the
future need."
Revised Forecast For Structured
ASICs
A few years ago, Gartner predicted a threefold increase over a two-year period in structured and platform ASIC revenues, going from $473 million in 2006 to
$1.45 billion in 2008 (). The revised
forecast shows revenues roughly doubling
over the next three years, winding up
around $828 million in 2009.
While this isn't as good as tripling revenue, this jump still far exceeds the rest of
the semiconductor industry, which is
expected to grow around 20% over the next
three years. So why isn't the outlook as
positive as originally forecasted?
The general feeling of folks in the
know is that the trust still isn't there, as
there's just too much risk revolving around structured ASICs. After all, quite
a few players in this market are relative
newcomers compared to the big hitters
in the ASIC foundry space, such as IBM
and TSMC. Lastly, structured ASICs do
tend to lag behind somewhat in process
technology offerings.
But eASIC has eliminated all objections
by offering a zero-NRE structured ASIC with
no minimum order quantity and a short
turnaround time. In fact, it will have an early offering of a 10 million-gate, 65-nm
structured ASIC later this quarter called
the Nextreme II. For now, the 5 million-gate
Nextreme NX5000 is available with a
plethora of drop-in intellectual property (IP)
and nearly 6 Mbits of RAM.
The interconnect is customized
through a single via layer generated using
a maskless electron beam lithography
approach called eBeam Direct-Write. This
method eliminates the need for custom
masks, removing the associated tooling
cost and shortening turnaround time.
This unique approach lets eASIC share
wafers among customers or projects by
printing different patterns on the same
wafer, meaning no minimum order quantity. Also, to mitigate risk, eASIC uses
Fujitsu's 90-nm process technology.
"The structured ASIC market is demonstrating a normalized cycle from hype to
ripe, where the message of ‘the new trend
in town' gained momentum and was
spread from the vendors to the media and
analysts to the users' community," says
Ronnie Vasishta, CEO of eASIC.
"There is an undeniable critical need
and a large potential market for a structured or platform ASIC solution. Now, we
are moving from the heavily publicized
domain to the normal course of business
where features and benefits win—in particular, price, power, low risk, and fast
time to production. This requires innovation and a truly disruptive technology,"
Vasishta continues.
"The window of opportunity is wide open
for a breakthrough structured ASIC that
can meet the customer's critical needs and
diminish the challenges of deep submicron
design and manufacturing," he notes.
So if the semiconductor industry has a
less than stellar year, no one will be able to
point the finger at FPGAs or structured
ASICs as the cause.