Large, fast, low-cost memory has been a boon to 32-bit MCUs, turning this market segment into one of the most competitive. Due to their larger die size, accelerators and processing peripherals can be included. FPGAs, DSP instructions, and coprocessors abound. Even Java byte-code acceleration can be found in standard components.
Many high-performance 32-bit microcontrollers (MCUs) follow the conventional MCU definition by incorporating nonvolatile memory with RAM and a host of peripherals, such as Motorola's 56F8300. Others minimize the amount of external hardware necessary to support external memory and peripherals. Another approach is to use a high-speed transport mechanism, such as HyperTransport and RapidIO. More often than not, on-chip peripherals tend to be more powerful than their 8- and 16-bit counterparts. Likewise, high-end 32-bit cores may have DSP, SIMD, or floating-point support. Some integrate these features into a single core while others turn to multiprocessing cores like Oki Semiconductor's ML67Q5200 (Fig. 1).
This level of optimization and integration has obvious payoffs in performance, but it can also yield better power utilization than low-end, 32-bit parts. Kevin Klien, standard products marketing manager for Motorola's 32-bit Embedded Controller Division, indicates that a high-performance, 32-bit part running at a slower speed often is a better choice than a less sophisticated, 32-bit MCU. In addition, completing a job more quickly and efficiently may allow the MCU to run in lower-power modes, like reduced clock speed or main power voltage, while a different MCU would need to continue running.
Effective use of on-chip peripherals and computational resources is what 32-bit MCUs do best. But, off-chip peripherals and communication are sometimes needed to exploit off-chip resources or coprocessors.
HIGH-PERFORMANCE INTERCONNECTS
A number of 32-bit MCUs incorporate Ethernet support, which provides a high-speed networking solution. However, it comes with significant software overhead. HyperTransport and RapidIO offer interconnects that match the performance of the core processor while requiring low communication overhead.
Intrinsity's FastMath and FastMIPS MCUs combine a high-speed MIPS-32 processing core with a pair of RapidIO ports (Fig. 2). They also support vector and matrix operations.
The 2-GHz FastMath chip incorporates a 4-by-4 SIMD array of 32-bit processing elements, each with its own local register file. The 1 Mbyte of on-chip memory is configurable as a layer 2 (L2) cache or SRAM. The dual RapidIO ports offer a 4-Gbyte/s aggregate throughput.
HyperTransport, which has appeared in more 64-bit MCUs than 32-bit MCUs, suits high-performance 32-bit MCUs. Nonetheless, RapidIO seems to have the edge in terms of the number of MCUs available with this communication option. RapidIO is also popular with 32-bit DSPs that have also been gaining more general-purpose processor support.
CUSTOM AUGMENTATION
Meeting high-performance application needs can be tough for a 32-bit MCU, even with the wide range of communication and on-chip peripherals. On-chip customization is one way to close that gap.
QuickLogic's solution combines an FPGA with a MIPS-32 processing core (Fig. 3). The FPGA can be used to augment I/O transfers or implement parallel-processing algorithms. Many algorithms, such as encryption, can be implemented more efficiently in hardware than in software. The FPGA can be reprogrammed on the fly, so multiple-part algorithms can be implemented in a step-wise fashion.
Although not strictly an MCU solution, Xilix and Altera provide large logic arrays that can be used to implement one or more 32-bit processors (Altera's Nios soft RISC processor is available in 16- and 32-bit versions). Thus, there's plenty of room for peripherals and custom logic. These companies have also been delivering more fixed solutions at a lower cost, implementing the systems originally programmed into the reprogrammable logic array parts.
Ubicom takes a software approach to peripherals (see "Hardware Scheduling Accelerates Soft Peripherals," p. 58). It includes a few standard peripherals like Ethernet multiply/add accumulates (MACs), but it provides others as virtual peripherals implemented as bit-banging device drivers. A very high-speed processor efficiently implements byte and bit processing, making the approach practical for a variety of peripheral implementations. The software approach allows for the creation of peripherals on demand and the implementation of complex algorithms, as opposed to QuickLogic's FPGA approach.
STANDARD ARM
One architecture that has been relatively devoid of standard parts is Arm. Initially found in custom system-on-a-chip (SoC) products, 32-bit Arm processors have gained a reputation for lower power consumption and high performance.
Lately there's been a flood of standard Arm-based MCUs from the likes of Sharp, STMicroelectronics, Philips Semiconductor, and Samsung. These standard parts span the architectural gamut from low-end 32-bit MCUs running the 16-bit Thumb instruction set to high-end Arm processors.
Standard Arm components have been available, though most have been customized for a particular application. AMD's Alchemy targets mobile devices. Also, Digi International's NetSilicon Net+Arm is designed for embedded network devices. In fact, it was one of the first to incorporate an Ethernet adapter and a bundled operating system.