IBM picked Synopsys to develop 45-nm USB PHY IF for its latest process node technology.
Synopsys' DesignWare USB 2.0 nanoPHY IP has built-in tuning circuits that enable post-silicon adjustments to account for unexpected chip or board parasitics or process variations without the need to modify the existing design. This feature enables designers to increase yield and minimize the cost of expensive silicon re-spins.
DesignWare also addresses key issues like low power consumption by implementing an architecture that provides an effective combination of small area, low power consumption and low leakage.
"High speed data connectivity IP is critical for customers using the latest process technologies," Ken Torino, director of foundry products for IBM Global Engineering Solutions, said in a statement.
Synopsys already provides USB PHY IP for IBM's 130-, 90-, and 65-nm process technologies. The company is the first IP provider to announce the development of a mixed-signal USB 2.0 PHY IP targeting this 45-nm process technology.
"Based on the past proven successes with Synopsys' DesignWare IP implemented in the Common Platform 90- and 65-nanometer processes, it is natural to extend the relationship to the development of 45-nanometer USB PHY IP," Torino added.