Interfacing FPGAs To High-Speed DRAMs Puts Designers To The Test

TIMING CHALLENGES
High-speed memory-interface design can take a lot of time, with numerous functional and timing requirements to be met. Minimizing clock jitter, channel-to-channel skew, duty-cycle distortion, and system noise all play an integral role in increasing the available timing margin, which in turn improves system reliability under all operating conditions. In addition, the DRAM state machine must be correctly implemented, and care must be taken for proper initialization and refresh of the DRAM cells.

Designers need to perform thorough verifications to ensure that the design meets all timing and functional requirements. Four categories of timing analysis must be performed: write data timing, address and command timing, read capture using DQS, and the resynchronization of captured read data to the system clock domain. For system-level verifications, behavioral models of DRAMs can be obtained from Denali Inc., the de facto memory-model provider to the industry.

To simplify the memory-interface design process and reduce design-cycle time, it's recommended that designers use memory-controller IP cores provided by FPGA vendors or third-party companies. Today's IP cores come with an easy-to-use graphic interface. They're parameterizable so designers can build a controller that fits their system requirements. For example, our DDR SDRAM controller core lets designers customize the controller to meet specific interface requirements, including clock speed, data bus width, number of chip selects, and memory properties.

In summary, high-speed memory interfaces are challenging to build, and designers need to consider several factors before designing these interfaces. Detailed timing analysis should be performed, and system-level verification is a must. Good quality memory-interface support alleviates design challenges and speeds up the design process. Selection of an FPGA for designing memory interfaces requires a thorough understanding of the hardware features supported in the FPGA and the support structure surrounding it. Memory IP controllers, software and tool support, simulation models, demonstration platforms, and good documentation are all critical for memory-interface design.