March Of The Multibus MCUs

Intellasys' SEAforth chip represents the extreme end of the spectrum (Fig. 4). It has 24 identical Forth microcontrollers linked in a 2D mesh. Each processor communicates with its nearest neighbors. The interfaces on the periphery of the mesh are conventional interfaces.

In essence, the outer processors are similar to the fido1100 UIC because they're programmable. Some overlap exists in capabilities, such as parallel and serial port support. But their purpose and designs diverge, as the UIC can handle Ethernet. Still, the Forth cores are programmable and very flexible.

This mesh architecture represents a logical plethora of buses within the chip, though the number of devices on the bus is limited. The communication interface chips are implemented more as a small bidirectional FIFO, since the bus in the processor core handles its processor and four interfaces.

As with the other architectures, each Forth core and the peripherals can be powered down to conserve power. In fact, the communication interfaces can wake up a processor so portions of the chip will turn on and off as data flows through the system.

Developers will need to take a closer look at processor architectures when choosing a platform. Faster clock speeds no longer guarantee better performance, and low-power modes don't guarantee power savings. The balance will make the difference. Understanding an application's requirements as well as the platform's capabilities will be important in creating products that can meet the demands of low power and high throughput.

Intellasys' SEAforth chip represents the extreme end of the spectrum (Fig. 4). It has 24 identical Forth microcontrollers linked in a 2D mesh. Each processor communicates with its nearest neighbors. The interfaces on the periphery of the mesh are conventional interfaces.

In essence, the outer processors are similar to the fido1100 UIC because they're programmable. Some overlap exists in capabilities, such as parallel and serial port support. But their purpose and designs diverge, as the UIC can handle Ethernet. Still, the Forth cores are programmable and very flexible.

This mesh architecture represents a logical plethora of buses within the chip, though the number of devices on the bus is limited. The communication interface chips are implemented more as a small bidirectional FIFO, since the bus in the processor core handles its processor and four interfaces.

As with the other architectures, each Forth core and the peripherals can be powered down to conserve power. In fact, the communication interfaces can wake up a processor so portions of the chip will turn on and off as data flows through the system.

Developers will need to take a closer look at processor architectures when choosing a platform. Faster clock speeds no longer guarantee better performance, and low-power modes don't guarantee power savings. The balance will make the difference. Understanding an application's requirements as well as the platform's capabilities will be important in creating products that can meet the demands of low power and high throughput.