Engineers are attracted to the flexibility of FPGAs and the ability to make major changes to their designs during testing and even in the field. These attributes are particularly important for emerging markets, where requirements are changing and there are no application-specific standard product (ASSP) solutions.
The performance of modern FPGAs has enabled these devices to target emerging markets, such as 100-Gbit Ethernet (100GbE) switches and Long-Term Evolution (LTE) basestations, that require very high performance. Engineers can reduce risk and development time by using application-specific intellectual property (IP).
FPGAs are good for markets that are underserved by ASSPs because the low volumes cannot justify the required investment for an ASSP. Additionally, FPGAs often are used on boards to provide glue logic or to bridge between different interconnects. This bridging may address the differences between the physical interfaces and the differences between protocols.
Finally, FPGAs are attractive for applications that need parallel digital-signal processing. These include wireless basestations, which need to process multiple data channels in parallel. In such cases, FPGAs can provide better prices and performance than general-purpose DSPs.
Some potential downsides of using an FPGA include a long development cycle and less efficient design than ASICs or ASSPs. The long design cycle results from designing at the gate level compared to using merchant silicon or developing software for a merchant processor. The gate efficiency results from having a generic layout that can be used for a diverse range of applications. Some current trends seek to address these issues in designing with FPGAs. Other trends focus on increasing the FPGA performance.
DESIGNING WITH FPGAs
The design process using an FPGA is far more complex than that using ASSPs or processors. To use FPGAs, a system designer must learn ASIC design tools instead of the more common and easier software-development tools required for processors. Relative to using an ASSP, using an FPGA takes longer and requires more resources. Even after the engineer becomes familiar with the tools, compiling the register transfer level (RTL) design can take a long time. Leading FPGA vendors offer partial configuration to help reduce compile times.
By making it easier to use FPGAs, vendors hope to increase the available target market for their devices. Altera and Xilinx have already developed tools that enable designers to go from DSP designs in Matlab to an FPGA design. Previously, this was a manual and error-prone task. Look for FPGA vendors to offer more sophisticated tools in the future.
Another approach to reducing development effort is raising the level of abstraction for the design. This task requires tools that let designers use high-level languages such as C and C++ instead of the current VHDL and Verilog. Although this concept is simple, in practice it has been difficult or impossible to accomplish effectively. Thus, the trend is more toward using a combination of VHDL/Verilog and C++, which uses pre-configured IP blocks. Impulse Accelerated is a leading exampleof a company that provides IP and the tools to enable design translation from C to FPGA.
Another way to reduce the development cycle is through the use of third-party IP or by embedding hard IP in the FPGA. For emerging applications such as 100GbE, third-party IP is critical. Often, this IP is first available on an FPGA before any other silicon. Sarance Technology is a good example of a third party delivering leading IP technology such as 40/100GbE media access controllers (MACs) and the Interlaken interface.
Yet another method of delivering IP is to embed it into the FPGA as a hard core. Embedded IP generally results in better die-area utilization and lower power dissipation, and it does not have licensing fees. If the designer does not use these IP blocks, however, the embedded IP is a waste of die area and power. So, FPGA vendors are careful to embed only IP that has broad applicability. Examples of embedded IP include PCI Express cores, Ethernet MACs, multiply-accumulate units, and DRAM controllers. In the next generation of FPGAs, likely embedded blocks will include USB and CPUs (ARM/MIPS).