In the Yellowstone signaling scheme, only the host controller needs to pack the FlexPhase adjustment circuits. The cost of the memories or other Yellowstone components is competitive, then, because they donÕt have to add the timing-control circuits. By enabling precise on-chip alignment of data with the clock, FlexPhase enables in-system timing characterization with margins accurate to within 2.5 ps.
Each data pin on the interface has unique data transmit and receive phases, and the phase values are determined at power-up. The transmit phase is set to deliver writes in quadrature with the sample clock at the receiver, while the receive phase is set to sample read data at the center of the data eye at time of arrival.
The Yellowstone interface is not a full bus architecture. Instead, it employs a point-to-point connection between the host chip and each data path on a Yellowstone device connected to the host. If multiple RAMs were connected to a memory controller, each RAMÕs data interface would have its own Yellowstone differential channels connected directly to the controller rather than share a common data bus.
In a typical double-data-rate (DDR) DRAM system, 128 data-bus signal lines must be routed and adjusted for signal delay if four 32-bit DDR DRAMs are used. In contrast, a system implemented with DRAMs and an ASIC host controller that all contain Yellowstone interfaces requires 16 differential channels per memory chip to achieve an aggregate memory bandwidth of 50 Gbytes/s. At the same time, a standard bus interface routes the address and clock signals to all the Yellowstone memory chips. So the pin count is comparable, but the board layout is much simpler as no pc-trace adjustments have to be made.
For more information, contact Rambus at www.rambus.com.