PAIR OF PowerPCs
Freescale's 1.5-GHz MPC8641D also packs a pair of e600 PowerPC processors onto one chip (Fig. 2). Its MPX bus coherency interface provides cache coherency support similar to that of the RM11200. But the MPC8641D uses a very fast parallel bus as its internal interconnect. If more cores are added in a future design, the bus performance must be increased, yet it's sufficient for the needs of two processors.
Like the RM11200, the MPC8641D gives each processor its own level 1 and level 2 cache. This is especially effective when the operating system supports processor affinity.
The MPC8641D shows its heritage with support for 1x or 4x Serial RapidIO instead of HyperTransport. One advantage of Serial RapidIO is that it can be used as a switched backplane technology. Each Serial RapidIO line operates at 2.5 Gbits/s. Serial RapidIO has found a home in the communications space, so expect many MPC8641Ds linked by a switch fabric, such as an AdvancedTCA 3.5-based system. A developer will have to forfeit one of the PCI Express interfaces to use Serial RapidIO.
The PCI Express interfaces can be set up individually as a root or endpoint at initialization time. As a result, the chip can act like a PCI Express peripheral itself or control one.
The other notable feature in Freescale's chip is found within each Gigabit Ethernet port. The ports can be set up as a simple 8-bit FIFO, or a pair can be linked as a 16-bit FIFO. When used as an Ethernet port, it supports TCP/IP checksum and IPv6 layer 4 hardware acceleration. The port also provides 16 quality-of-service queues. Layer 2 features include VLAN insertion and deletion per frame and a 16-exact-match MAC address table.
MULTIPLE QUADS
Broadcom's 1.2-GHz BCM1480 represents a more advanced version of its BCM1250 (Fig. 3). The BCM1480 brings significant enhancements, including three SPI-4/HyperTransport (HT) links with ccNUMA (cache coherent NUMA) support. The latter operates in a fashion similar to AMD's Opteron processors, allowing a multichip, multiprocessor system to be constructed without additional glue logic. It's simply a matter of hooking the chips together via the HT links. There's a delay in accessing remote memory, but most accesses are a single HT hop away. Combine this with large caches to minimize overhead for off-chip access.
Designers can choose the necessary mix of SPI-4 and HT links. The HT links can be used to access HT peripherals or memory on another BCM1480. Three ports allow designers to create a number of different configurations from a mesh of processors or SPI-4 interconnects to a bridge between the two interfaces. The BCM1480 should find homes in SPI-4 packet-processing applications.
Expect more multicore chips and matching application software in the next few years. The trend is in place and will continue to unfold.
Broadcom
www.broadcom.com
Freescale
www.freescale.com
PMC Sierra
www.pmc-sierra.com