Flash memory, the dominant technology for nonvolatile storage, has constantly improved over the last 20 years, with still further enhancements expected over the next decade. But emerging nonvolatile technologies promise to deliver higher performance and greater endurance than flash memory. These new technologies—based on Ovonic, ferroelectric, and magnetic
materials—offer different benefits, enabling designers to better match a technology to their application (see the table "Comparison of Non-Flash Technologies").
FLASH STILL SIZZLES
The extremely thin-oxide (ETOX) technology used by most suppliers of NOR- and NAND-based flash memory is moving into what Intel calls its eighth generation as feature dimensions shrink to 0.13 µm. Several companies have already developed next-generation 90-nm processes that will squeeze 2 Gbits of NAND-based storage onto one chip. Earlier this year, Samsung Semiconductor disclosed details of a single-bit/cell 2-Gbit chip that can run from a 1.8-V supply. It will offer a block erase time of 2 ms, a page program time of 300 ms, and a read access time of 25 ms for the first access and 50 ns per subsequent access during a burst cycle.
Competing with the thin-oxide structures, a thick-oxide memory cell developed by Silicon Storage Technology, dubbed SuperFlash, serves the moderate density flash requirements, currently up to 16 Mbits/chip and shortly moving to 32 and 64 Mbits. The cell's main advantages include a fast store time and simple manufacturing process that's very easy to integrate into the standard process flow for CMOS digital and mixed-signal products.
A multilevel-charge (MLC) storage scheme, developed by designers at Intel and now several other companies, doubles a memory array's storage capacity. The MLC scheme divides the stored charge in the cell into four levels. Then, using three comparators, it can determine the charge value of the charge and thus the level it matches. By assigning values of 00, 01, 10, and 11 to the four levels, the charge value will determine the bit representations.
Initially applied to NOR-style memories by Intel, suppliers such as M-Systems/Toshiba, Samsung, SanDisk, and Hitachi (now Renesas Technology) have applied their versions of the MLC approach to NAND-based (or AND-based) memory architectures. Hitachi recently demonstrated a 1-Gbit MLC AND-based flash memory that has a 10-Mbyte/s programming speed. To help keep the chip size under 95 mm2 when produced using 0.13-µm design rules, the company developed an assisted-gate AND-type memory structure and a very compact SRAM write buffer. The fast programming speed is possible thanks to a constant-charge-injection programming technique. This reduces the programming time by 20-fold versus conventional AND arrays.
Back to NOR-style memories, the MLC technology was most recently applied to create a 128-Mbit device fabricated with 0.13-µm design rules. The prototype chip from Intel actually contains 64 million cells squeezed into a chip area of 27.3 mm2. It can operate from a 1.8-V supply and performs read operations in just 55 ns. Subsequent burst-read operations can be done at 125 MHz, making this memory device the fastest flash memory to date. Commercial samples of the chip are available.
Intel won't stop at two bits per cell. Already, research is under way to determine if four bits per cell would be technically practical. That would require 16 charge levels to be defined in the memory cell, and those levels must remain stable over temperature and other system conditions. This might still be several years from commercialization.
Competing with the MLC technology is a nitride-oxide memory cell structure developed by Saifun Semiconductor. The NROM cell can also store two bits, effectively doubling the bit capacity of memories based on the cell. Advanced Micro Devices (AMD) and Fujitsu have collaborated with and invested in Saifun, and both are developing families of flash-memory devices based on what AMD calls the MirrorBit technology.
Rather than use different levels of charge to represent the bits, the MirrorBit scheme can independently store two full-margin charges, one on each end of the transistor gate in each storage cell (Fig. 1). Then, a sensing scheme can detect whether or not a charge is present on either end of the gate to read either bit, or both bits. AMD says that this approach is inherently more reliable than the MLC scheme because the full charge is used for each bit.
Also applied to NOR-architecture flash memories, the MirrorBit technology will let AMD manufacture chips with capacities ranging from 16 to 256 Mbits. As lithography features continue to shrink, the technology is expected to achieve densities of 1 Gbit per chip by late 2004. In contrast, Strataflash MLC devices from Intel are available in capacities of up to 128 Mbits, with 256-Mbit devices expected in late 2003.
Flash memory, the dominant technology for nonvolatile storage, has constantly improved over the last 20 years, with still further enhancements expected over the next decade. But emerging nonvolatile technologies promise to deliver higher performance and greater endurance than flash memory. These new technologies—based on Ovonic, ferroelectric, and magnetic
materials—offer different benefits, enabling designers to better match a technology to their application (see the table "Comparison of Non-Flash Technologies").
FLASH STILL SIZZLES
The extremely thin-oxide (ETOX) technology used by most suppliers of NOR- and NAND-based flash memory is moving into what Intel calls its eighth generation as feature dimensions shrink to 0.13 µm. Several companies have already developed next-generation 90-nm processes that will squeeze 2 Gbits of NAND-based storage onto one chip. Earlier this year, Samsung Semiconductor disclosed details of a single-bit/cell 2-Gbit chip that can run from a 1.8-V supply. It will offer a block erase time of 2 ms, a page program time of 300 ms, and a read access time of 25 ms for the first access and 50 ns per subsequent access during a burst cycle.
Competing with the thin-oxide structures, a thick-oxide memory cell developed by Silicon Storage Technology, dubbed SuperFlash, serves the moderate density flash requirements, currently up to 16 Mbits/chip and shortly moving to 32 and 64 Mbits. The cell's main advantages include a fast store time and simple manufacturing process that's very easy to integrate into the standard process flow for CMOS digital and mixed-signal products.
A multilevel-charge (MLC) storage scheme, developed by designers at Intel and now several other companies, doubles a memory array's storage capacity. The MLC scheme divides the stored charge in the cell into four levels. Then, using three comparators, it can determine the charge value of the charge and thus the level it matches. By assigning values of 00, 01, 10, and 11 to the four levels, the charge value will determine the bit representations.
Initially applied to NOR-style memories by Intel, suppliers such as M-Systems/Toshiba, Samsung, SanDisk, and Hitachi (now Renesas Technology) have applied their versions of the MLC approach to NAND-based (or AND-based) memory architectures. Hitachi recently demonstrated a 1-Gbit MLC AND-based flash memory that has a 10-Mbyte/s programming speed. To help keep the chip size under 95 mm2 when produced using 0.13-µm design rules, the company developed an assisted-gate AND-type memory structure and a very compact SRAM write buffer. The fast programming speed is possible thanks to a constant-charge-injection programming technique. This reduces the programming time by 20-fold versus conventional AND arrays.
Back to NOR-style memories, the MLC technology was most recently applied to create a 128-Mbit device fabricated with 0.13-µm design rules. The prototype chip from Intel actually contains 64 million cells squeezed into a chip area of 27.3 mm2. It can operate from a 1.8-V supply and performs read operations in just 55 ns. Subsequent burst-read operations can be done at 125 MHz, making this memory device the fastest flash memory to date. Commercial samples of the chip are available.
Intel won't stop at two bits per cell. Already, research is under way to determine if four bits per cell would be technically practical. That would require 16 charge levels to be defined in the memory cell, and those levels must remain stable over temperature and other system conditions. This might still be several years from commercialization.
Competing with the MLC technology is a nitride-oxide memory cell structure developed by Saifun Semiconductor. The NROM cell can also store two bits, effectively doubling the bit capacity of memories based on the cell. Advanced Micro Devices (AMD) and Fujitsu have collaborated with and invested in Saifun, and both are developing families of flash-memory devices based on what AMD calls the MirrorBit technology.
Rather than use different levels of charge to represent the bits, the MirrorBit scheme can independently store two full-margin charges, one on each end of the transistor gate in each storage cell (Fig. 1). Then, a sensing scheme can detect whether or not a charge is present on either end of the gate to read either bit, or both bits. AMD says that this approach is inherently more reliable than the MLC scheme because the full charge is used for each bit.
Also applied to NOR-architecture flash memories, the MirrorBit technology will let AMD manufacture chips with capacities ranging from 16 to 256 Mbits. As lithography features continue to shrink, the technology is expected to achieve densities of 1 Gbit per chip by late 2004. In contrast, Strataflash MLC devices from Intel are available in capacities of up to 128 Mbits, with 256-Mbit devices expected in late 2003.