In an effort to resolve some related issues, Galileo Technology Inc. has unveiled a set of chips targeted at the converged network. The chip set performs the functions of the Layer 2 switch, Layer 3 switch/router, Layer 2/3/4/5 bandwidth shaper, and Layer 2/3/4/5 firewall. Each of the layers performs at full wire speed, too. The set also provides full AoS on a voice-over-IP switch. (See "Voice/Data-Switch Processor Guarantees 'Availability Of Service,'" electronic design, Nov. 22, 1999, p. 57).
To achieve the AoS capability, the GalNet 3 chip set borrows ATM's ideas of traffic policing a policy enforcement and dedicating bandwidth to specific flows (such as voice packets). Those steps guarantee both AoS and QoS. The circuits also improve on ATM by allowing the network to make informed AoS/QoS decisions based on the packet's data contents.
ATM systems can only do this at connection setup time. Once the connection is established, the bandwidth is dedicated—whether it's being used or not. The GalNet solution lets unused bandwidth be "reclaimed" and applied to other applications.
Managing the packet flow around a network is key to ensuring efficient operation and maximizing available bandwidth. Many companies are crafting first- and second-generation network processors that will form the heart of next-generation routers. As network traffic increases, classifying and routing the IP flow demands higher performance and more intelligence to prevent bottlenecks from slowing packet movements. CPU-powered routers traditionally handled such tasks, but their software overheads can bog down the routing process.
Custom architectures like the one developed by Entridia Corp. hold the promise of greatly accelerated packet movement. By placing the routing algorithms in silicon as hardwired operations, the company's Wisper chip (wire-speed edge router) can perform routing at 6 Gbits/s. On-chip routing engines reduce the latency typically encountered when those algorithms are executed on a host processor.
In the networks, both the routers and switches are vital to moving data. Typically, Layer 3 switches are used in the enterprise. They help simplify IP packet forwarding and achieve wire-speed operation. But switches haven't replaced routers at the edge of the network. There, the router's ability to handle multiple services and its higher network intelligence are critical to maintaining maximum throughput.
Since their inception, routers have usually employed hardware to handle packet forwarding and software for packet processing. But then packet processing becomes the bottleneck, and that's where many of the network processors shine as data rates start to hit the terabit level. Still higher data rates can be expected in the next few years, as data requirements inch toward the pentabit-per-second level.
For fast packet processing, CAM technology has long been used to accelerate the matching process. Due to the large chip area required for the memory array, however, these devices come with a high price tag. That's changing with the CAM approaches released last year.
A ternary CAM created by NetLogic allows the use of large lookup tables with user-definable widths of 72, 144, or 288 bits. Rather than offer just the binary 0 and 1 evaluation capability, ternary CAMs can perform compare operations on bits that are 1, 0, or "don't care." That's because the user is able to mask an entry on a per-bit basis. This capability is essential in network-routing applications, where the longest prefix-match searches are used in either classless interdomain routing or subnet masking applications.
Layer 3 and Layer 4 routing applications also can benefit from the mask-per-bit capability by letting users attach various policies and priorities to the router address-table entries. Such a scheme dramatically simplifies router design and can improve the time-to-market for the end product.
There are new techniques helping to speed network traffic that don't use CAM technology. Specialized chips perform fast pattern processing, like the recently released FPP chip from Agere. That chip performs high-speed bit-stream processing and is controlled by a very-high-level programming language that makes it simple to code the application and maximize code reuse.
Able to provide throughputs at OC-48 speeds with only a 133-MHz clock, the processor will deliver still higher throughputs when implemented in more advanced CMOS processes. This chip is one of several in a set designed by the company to perform 2.5-Gbit/s, wire-speed, Layer 3 packet/cell processing. It also can implement a virtual segmentation and reassembly process for internetworking applications.
With such an abundance of choices in network processors and switch fabrics, designers will be able to implement wire-speed solutions for the forthcoming generations of OC-48 systems. Future chip generations promise wire-speed operation at 10 Gbits/s. But that may take another year or two. Beyond that, yet another architecture may be needed to handle 40-Gbit/s and faster data-transmission requirements.
In an effort to resolve some related issues, Galileo Technology Inc. has unveiled a set of chips targeted at the converged network. The chip set performs the functions of the Layer 2 switch, Layer 3 switch/router, Layer 2/3/4/5 bandwidth shaper, and Layer 2/3/4/5 firewall. Each of the layers performs at full wire speed, too. The set also provides full AoS on a voice-over-IP switch. (See "Voice/Data-Switch Processor Guarantees 'Availability Of Service,'" electronic design, Nov. 22, 1999, p. 57).
To achieve the AoS capability, the GalNet 3 chip set borrows ATM's ideas of traffic policing a policy enforcement and dedicating bandwidth to specific flows (such as voice packets). Those steps guarantee both AoS and QoS. The circuits also improve on ATM by allowing the network to make informed AoS/QoS decisions based on the packet's data contents.
ATM systems can only do this at connection setup time. Once the connection is established, the bandwidth is dedicated—whether it's being used or not. The GalNet solution lets unused bandwidth be "reclaimed" and applied to other applications.
Managing the packet flow around a network is key to ensuring efficient operation and maximizing available bandwidth. Many companies are crafting first- and second-generation network processors that will form the heart of next-generation routers. As network traffic increases, classifying and routing the IP flow demands higher performance and more intelligence to prevent bottlenecks from slowing packet movements. CPU-powered routers traditionally handled such tasks, but their software overheads can bog down the routing process.
Custom architectures like the one developed by Entridia Corp. hold the promise of greatly accelerated packet movement. By placing the routing algorithms in silicon as hardwired operations, the company's Wisper chip (wire-speed edge router) can perform routing at 6 Gbits/s. On-chip routing engines reduce the latency typically encountered when those algorithms are executed on a host processor.
In the networks, both the routers and switches are vital to moving data. Typically, Layer 3 switches are used in the enterprise. They help simplify IP packet forwarding and achieve wire-speed operation. But switches haven't replaced routers at the edge of the network. There, the router's ability to handle multiple services and its higher network intelligence are critical to maintaining maximum throughput.
Since their inception, routers have usually employed hardware to handle packet forwarding and software for packet processing. But then packet processing becomes the bottleneck, and that's where many of the network processors shine as data rates start to hit the terabit level. Still higher data rates can be expected in the next few years, as data requirements inch toward the pentabit-per-second level.
For fast packet processing, CAM technology has long been used to accelerate the matching process. Due to the large chip area required for the memory array, however, these devices come with a high price tag. That's changing with the CAM approaches released last year.
A ternary CAM created by NetLogic allows the use of large lookup tables with user-definable widths of 72, 144, or 288 bits. Rather than offer just the binary 0 and 1 evaluation capability, ternary CAMs can perform compare operations on bits that are 1, 0, or "don't care." That's because the user is able to mask an entry on a per-bit basis. This capability is essential in network-routing applications, where the longest prefix-match searches are used in either classless interdomain routing or subnet masking applications.
Layer 3 and Layer 4 routing applications also can benefit from the mask-per-bit capability by letting users attach various policies and priorities to the router address-table entries. Such a scheme dramatically simplifies router design and can improve the time-to-market for the end product.
There are new techniques helping to speed network traffic that don't use CAM technology. Specialized chips perform fast pattern processing, like the recently released FPP chip from Agere. That chip performs high-speed bit-stream processing and is controlled by a very-high-level programming language that makes it simple to code the application and maximize code reuse.
Able to provide throughputs at OC-48 speeds with only a 133-MHz clock, the processor will deliver still higher throughputs when implemented in more advanced CMOS processes. This chip is one of several in a set designed by the company to perform 2.5-Gbit/s, wire-speed, Layer 3 packet/cell processing. It also can implement a virtual segmentation and reassembly process for internetworking applications.
With such an abundance of choices in network processors and switch fabrics, designers will be able to implement wire-speed solutions for the forthcoming generations of OC-48 systems. Future chip generations promise wire-speed operation at 10 Gbits/s. But that may take another year or two. Beyond that, yet another architecture may be needed to handle 40-Gbit/s and faster data-transmission requirements.