Overcome Traditional Memory-Speed Barriers With Embedded DRAM

For applications where performance is of primary importance, designers have traditionally chosen SRAM technology over DRAM. Although commodity DRAM offers much higher density and a lower cost per bit, it has been a slower memory technology than SRAM. In the past, many applications were prepared to pay a significant premium for SRAM performance.

With the availability of embedded DRAM processes, it's now possible to achieve performance levels approaching those of SRAM while retaining significant density advantages. Designers no longer need to choose between density or speed. An embedded DRAM macrocell architected for performance can achieve random-access cycle times beyond 200 MHz, with a bit density five to 10 times greater than SRAM.

While a DRAM bit cell requires only a single transistor and capacitor, an SRAM cell uses six n- and p-channel transistors, resulting in a 10:1 density advantage for DRAM. SRAM has a fundamental speed advantage because the 6T cell can drive a signal toward the output. A DRAM cell, in contrast, is a passive circuit that must be carefully sensed before a logic level can be passed on to successive stages of logic.

Figure 1 shows the basic circuitry at the core of a DRAM array. Individual memory cells consist of an n-channel transistor controlled by a wordline (WL), which selectively connects a bit storage capacitor to a bitline (BL). A logic 0 or a logic 1 is stored as V_SS or V_DD levels on the storage capacitor.

During quiescent periods, the bitlines are held at a midrail potential or V_DD/2. When one of the wordlines is enabled at the beginning of a memory access, the voltage stored in the accessed cell capacitor is attenuated by the ratio of cell capacitance to bitline capacitance.

Since the bitline capacitance is roughly an order of magnitude greater than the cell capacitance, the data magnitude on the bitlines is only a few hundred millivolts above or below V_DD/2. For this reason, a bitline sense amplifier is needed to amplify the bitline voltage to a full-rail signal. The signal path after the bitline sense amplifier is very much like an SRAM. This requirement to perform bitline sensing to amplify a small signal from a passive bit cell accounts for the fundamental difference between DRAM and SRAM access-time performance.

To complete the DRAM read cycle, the data must be written back to the memory cell. Unlike SRAM, a DRAM read is destructive. The bitline sense amplifier is a regenerative latch that amplifies the bitline potential to full rail. To restore this level on the memory-cell capacitor, the n-channel access transistor must be fully turned on. To store a V_DD level in the memory cell, the wordline must be raised to a potential greater than V_DD + V_T, where V_T is the transistor threshold voltage.

In a modern DRAM, on-chip charge pumps and level shifters generate the required wordline voltages. DRAM devices must be able to withstand voltages higher than V_DD, though, resulting in larger device dimensions and poorer transistor performance. For cost reasons, commodity DRAMs have only a single type of transistor, which must be used throughout the critical path. For a given process generation, commodity SRAM will have a performance advantage over commodity DRAM, because SRAM circuits do not have to deal with voltages higher than V_DD.

For applications where performance is of primary importance, designers have traditionally chosen SRAM technology over DRAM. Although commodity DRAM offers much higher density and a lower cost per bit, it has been a slower memory technology than SRAM. In the past, many applications were prepared to pay a significant premium for SRAM performance.

With the availability of embedded DRAM processes, it's now possible to achieve performance levels approaching those of SRAM while retaining significant density advantages. Designers no longer need to choose between density or speed. An embedded DRAM macrocell architected for performance can achieve random-access cycle times beyond 200 MHz, with a bit density five to 10 times greater than SRAM.

While a DRAM bit cell requires only a single transistor and capacitor, an SRAM cell uses six n- and p-channel transistors, resulting in a 10:1 density advantage for DRAM. SRAM has a fundamental speed advantage because the 6T cell can drive a signal toward the output. A DRAM cell, in contrast, is a passive circuit that must be carefully sensed before a logic level can be passed on to successive stages of logic.

Figure 1 shows the basic circuitry at the core of a DRAM array. Individual memory cells consist of an n-channel transistor controlled by a wordline (WL), which selectively connects a bit storage capacitor to a bitline (BL). A logic 0 or a logic 1 is stored as V_SS or V_DD levels on the storage capacitor.

During quiescent periods, the bitlines are held at a midrail potential or V_DD/2. When one of the wordlines is enabled at the beginning of a memory access, the voltage stored in the accessed cell capacitor is attenuated by the ratio of cell capacitance to bitline capacitance.

Since the bitline capacitance is roughly an order of magnitude greater than the cell capacitance, the data magnitude on the bitlines is only a few hundred millivolts above or below V_DD/2. For this reason, a bitline sense amplifier is needed to amplify the bitline voltage to a full-rail signal. The signal path after the bitline sense amplifier is very much like an SRAM. This requirement to perform bitline sensing to amplify a small signal from a passive bit cell accounts for the fundamental difference between DRAM and SRAM access-time performance.

To complete the DRAM read cycle, the data must be written back to the memory cell. Unlike SRAM, a DRAM read is destructive. The bitline sense amplifier is a regenerative latch that amplifies the bitline potential to full rail. To restore this level on the memory-cell capacitor, the n-channel access transistor must be fully turned on. To store a V_DD level in the memory cell, the wordline must be raised to a potential greater than V_DD + V_T, where V_T is the transistor threshold voltage.

In a modern DRAM, on-chip charge pumps and level shifters generate the required wordline voltages. DRAM devices must be able to withstand voltages higher than V_DD, though, resulting in larger device dimensions and poorer transistor performance. For cost reasons, commodity DRAMs have only a single type of transistor, which must be used throughout the critical path. For a given process generation, commodity SRAM will have a performance advantage over commodity DRAM, because SRAM circuits do not have to deal with voltages higher than V_DD.