The dsPIC provides a full set of 16 vectored interrupts—one Reset, seven nonmaskable traps, and eight prioritized general interrupts. All operations, both MCU and DSP, are interruptible. DSP operations are stopped, and the controlling register values stored, to restart the DSP function. Traps are ordered into a fixed priority scheme
For Fast interrupts, the processor relies on shadowing, such as a fast backup for the W, PC, Data Table Page Address, Data Space Program Page Address, and Repeat Loop Counter registers. Basically, the hardware maintains an active and a shadow set of registers. On an interrupt, the hardware directly loads the shadow registers in parallel, eliminating the time to sequentially save the register context. Fast Interrupts, though, are only one level deep. Any more would lose register context.
Interrupt Latency for Fast Interrupts is one cycle. On the second clock cycle, the hardware executes the first instruction in the Interrupt Service Routine (ISR). But for standard interrupts—both one- and two-word instructions—interrupt latency is on the order of three clock cycles.
Price & Availability
dsPIC Beta sampling will begin in the fourth quarter of this year, with production in the first quarter of 2002. Cost is $3 to $9 in lots of 10,000. Microchip projects a 20-chip family by the first quarter of 2002.
Microchip Technology, 2355 W. Chandler Blvd., Chandler, AZ 85224; (480) 792-7200; www.microchip.com.
FUNCTION24-bit instruction, 16-bit datapath
Superset of 8-bit PIC18xxxx
16- by 16-bit general register set
Full DSP capability
Two 40-bit accumulators
16- by 16-bit multiplier
40-bit barrel shifter
Dual X, Y accesses per clock cycle
Zero-overhead MAC loops
4-kbyte data RAM
32-kbyte flash code memory
PERFORMANCE30-MHz clock
30 MIPS peak, 25 MIPS typical
Prefetch stage, execution stage
Most instructions execute in one cycle
Two-cycle execution for branches
One-cycle 16- by 16-bit multiply
DO loop instruction
Repeat instruction
ON-CHIP PERIPHERALSFour 16-bit timer/counters
Serial SPI port (8-, 18-bit transfers)
I2C serial port (100 kHz, 400 kHz, 1 MHz)
UART, CAN bus interface
12-bit ADC (100 ksamples/s, 16-word sample buffer)
PWM, quadrature encoder
Codec interface
Oscillator and power management
Dynamic flash memory loading
The dsPIC provides a full set of 16 vectored interrupts—one Reset, seven nonmaskable traps, and eight prioritized general interrupts. All operations, both MCU and DSP, are interruptible. DSP operations are stopped, and the controlling register values stored, to restart the DSP function. Traps are ordered into a fixed priority scheme
For Fast interrupts, the processor relies on shadowing, such as a fast backup for the W, PC, Data Table Page Address, Data Space Program Page Address, and Repeat Loop Counter registers. Basically, the hardware maintains an active and a shadow set of registers. On an interrupt, the hardware directly loads the shadow registers in parallel, eliminating the time to sequentially save the register context. Fast Interrupts, though, are only one level deep. Any more would lose register context.
Interrupt Latency for Fast Interrupts is one cycle. On the second clock cycle, the hardware executes the first instruction in the Interrupt Service Routine (ISR). But for standard interrupts—both one- and two-word instructions—interrupt latency is on the order of three clock cycles.
Price & Availability
dsPIC Beta sampling will begin in the fourth quarter of this year, with production in the first quarter of 2002. Cost is $3 to $9 in lots of 10,000. Microchip projects a 20-chip family by the first quarter of 2002.
Microchip Technology, 2355 W. Chandler Blvd., Chandler, AZ 85224; (480) 792-7200; www.microchip.com.
FUNCTION24-bit instruction, 16-bit datapath
Superset of 8-bit PIC18xxxx
16- by 16-bit general register set
Full DSP capability
Two 40-bit accumulators
16- by 16-bit multiplier
40-bit barrel shifter
Dual X, Y accesses per clock cycle
Zero-overhead MAC loops
4-kbyte data RAM
32-kbyte flash code memory
PERFORMANCE30-MHz clock
30 MIPS peak, 25 MIPS typical
Prefetch stage, execution stage
Most instructions execute in one cycle
Two-cycle execution for branches
One-cycle 16- by 16-bit multiply
DO loop instruction
Repeat instruction
ON-CHIP PERIPHERALSFour 16-bit timer/counters
Serial SPI port (8-, 18-bit transfers)
I2C serial port (100 kHz, 400 kHz, 1 MHz)
UART, CAN bus interface
12-bit ADC (100 ksamples/s, 16-word sample buffer)
PWM, quadrature encoder
Codec interface
Oscillator and power management
Dynamic flash memory loading