Virtex II supports add-on IP, too. Any programmable-gate area can be re-moved and then substituted by hard IP. This IP can use the same local and hierarchical routing resources as did the logic that it replaced.
Altera also is in the programmable-SoC competition with its Apex series, which fields up to 2.4 Mgates. These FPGAs are RAM-based, built on a LUT-based logic cell, with hierarchical routing to handle large datapath widths. They can tolerate 200-MHz internal clock rates, and up to 622 MHz for serial I/O. The architecture will support hard ARM, MIPS IP cores, and the AMBA bus.
Another product line, Altera's Excalibur FPGA, supports high-end SoC design. This is a SRAM-based FPGA using LUT-based logic cells (Fig. 4). It handles up to 1M usable gates, with up to 128 kbytes of dual-port SRAM. Excalibur FPGAs can incorporate a MIPS or ARM µprocessor. It uses ARM's AMBA busing system to integrate the processor with on-chip peripherals and logic.
Programmable logic started out as a mechanism to implement control logic. As logic densities increased and newer CPLD/FPGA technologies emerged, programmable logic increasingly took on more datapath chores. Today's higher-density CPLDs and FPGAs have the majority of their logic dedicated to datapath functions. In many designs (50 kgates and over), at least 90% to 95% of the implemented logic performs datapath functions. Most designs, then, consist of dataflow datapaths controlled by a small subset of control logic.
Early combinatorial PALs and later PLDs have given way to CPLDs and FPGAs. PLDs are still around, but today's CPLDs and FPGAs deliver higher gate densities and clock rates. CPLDs tend to follow the PLD model, building on logic blocks of combinatorial logic and flip-flops interconnected via a central switch.
In contrast, FPGAs usually rely on distributed and hierarchical routing resources, connecting logic cells. These logic-cell implementations vary from one vendor to the next. Some, like Xilinx, rely on a LUT or LUT-based logic element with an output flip-flop. Others have a combinatorial logic cell, such as QuickLogic's large input, multiplexer-based logic cell with an output flip-flop. The programmable interconnects range from fuse and antifuse to memory-based connections, using SRAM, flash, or EEPROM configuration memory. The trend in higher-end FPGAs has been toward hierarchical routing, implementing a mix of nearest-neighbor, local, and global routing resources.
As serial-data-input clock rates climb, FPGAs will work with wider and wider datapaths needed to "parallelize" the serial input for processing using its slower internal clocks. FPGA cells' bit widths are slowly starting to widen to handle larger datapaths. For example, the latest Xilinx FPGA, the Virtex II, has widened its Configurable Logic Blocks (CLBs). It integrates a stack of four slices interfacing to a switch matrix. Making up the basic slice are two function generators, each containing a four-input LUT, a multiplexer, and a flip-flop.
Similarly, Agere's ORCA Series 4, designed for datapath implementations, has a wide logic implementation. The basic logic element is the programmable function unit (PFU), which is organized as twin sets of four four-input LUTs and four latches/flip-flops, with a spare flip-flop for the PFU.
Today's CPLDs have gone beyond combinatorial logic and state-machine implementations. They're often used to configure and operate on datapaths, such as multiplexing signal lines, or to operate on datapath elements at bus speeds. Some CPLD densities are pushing 500,000 system gates and higher. Cypress' Delta39K CPLD integrates up to 505,000 gates (3840 macrocells) with up to a 672-kbit cluster and a 168-kbit channel memory, plus 512 I/O pins. The CPLD clocks in at 154 MHz, and even higher for less dense parts.
CPLDs also supply fast switching for datapath elements. For instance, Lattice's ispLSI 2000VE family of CPLDs deliver 3-ns pin-to-pin switching, used to multiplex and operate on moving data. The CPLD's internal logic clocks at up to 300 MHz and supports up to 192 macrocells.