LOGISTICAL ASPECTS
For every unit to be built, the owner of the
design (OEM) must provide one properly
preprogrammed secure memory
to the contract manufacturer (CM) that
makes the product with the embedded
FPGA. This one-to-one relationship limits
the number of authorized units that
the CM can build. To prevent the CM
from tampering with the secure memory
(e.g., claiming that additional memories
are needed because some were not
programmed properly), it’s advisable to
write-protect the secret key.
There’s no need to worry about the
security of the 1-Wire EEPROM data
memory, even if it’s not write-protected.
By design, this memory data can only
be changed by individuals who know the
secret key. As a welcome side effect, this
characteristic enables the application
designer to implement soft-feature management—
the FPGA can enable/disable
functions depending on data that it reads
from the SHA-1 secured memory.
It’s not always practical for the OEM
to preprogram memory devices before
delivery to the CM. To address this situation,
the manufacturer of the secure
memory could set up a SHA-1 secret
and EEPROM-array preprogramming
service for the OEM. Maxim provides
such a service, where secure memory
devices are registered and configured at
the factory according to OEM input and
then shipped directly to the CM. Key
benefits of such a service include:
• Eliminating the need for the OEM to
disclose the secret key to the CM.
• Eliminating the need for the OEM to
implement its own preprogramming
system.
• Only OEM-authorized third parties
have access to registered devices.
• The vendor maintains records of
shipped quantities if needed for OEM
auditing purposes.
PROOF OF CONCEPT
The FPGA security method featured in
this article has been tested with products
from Altera and Xilinx. In its whitepaper
“An FPGA Design Security Solution
Using a Secure Memory Device,”
Altera concludes, “This FPGA design
security IFF solution protects Altera
FPGA designs from being cloned even
if the configuration data bit stream is captured. The user design remains disabled
until the hash algorithm computation
in both the FPGA and the secure
memory match. This design security
solution protects FPGA designer’s IP.”3
Similarly, Xilinx states in its application
note XAPP780: “The system’s security is
fundamentally based on the secrecy of
the secret key and loading of the key in
a secure environment. This entire reference
design, except the secret key, is
public abiding by the widely accepted
Kerckhoffs’ law. The simple interface to
programming and authentication provided
in this application note make this
copy protection scheme very easy to
implement.”4 (In his groundbreaking article
on military cryptography, the Flemish
linguist Auguste Kerckhoffs argued that
instead of relying on obscurity, security
should depend on the strength of
keys, because in the event of a breach,
only the keys would need to be replaced
instead of the whole system.)
CONCLUSION
Protection against piracy of intellectual
property requires adding just one lowcost
chip (DS28E01 < $1.00 at 10k
units) and updates to the FPGA configuration
code. Thanks to the 1-Wire
interface, only a single FPGA pin is taken
for security purposes. (If more pins
are available on the FPGA, the I2C version
of the secure memory can be used
in lieu of the 1-Wire version. This would
also necessitate some changes to the
FPGA configuration pattern as well as
the control software for the embedded
microcontroller.)
The secure memories are able to be
ordered preprogrammed with either a
fixed or computed secret key and application-
specific data. Preprogrammed
parts then get shipped only to the OEM,
or possibly to authorized contract manufacturers,
and they can only build as
many units as preprogrammed parts
are available.
References:
1. Drimer, Saar, “Volatile FPGA design security
– a survey,” work in progress, http://www.cl.cam.ac.uk/~sd410/papers/fpga_security.pdf
2. Secure Hash Standard, http://www.itl.nist.gov/fipspubs/fip180-1.htm
3. Altera White Paper 01033: “An FPGA Design
Security Solution Using a Secure Memory
Device,” http://www.altera.com/literature/wp/wp-01033.pdf
4. Xilinx Application Note XAPP780: “FPGA
IFF Copy Protection Using Dallas Semiconductor/
Maxim DS2432 Secure EEPROMs,” http://www.xilinx.com/support/documentation/application_notes/xapp780.pdf