Also, the circuitry occupies a miniscule amount of chip area when it's embedded in a chip—less than 4 square mils when fabricated with 0.5-µm design rules. That area is pretty much the same as a bonding pad. But it saves some area as the cell can replace the ESD protection circuitry too, at no extra cost. This is because ESD protection is included in the cell structure. So, using the EZterm cells has a negligible impact on chip area and power.
The nonlinear circuits can self-adjust to the use of connectors and sockets too, as well as the variable loading that they can create. For example, a high-speed memory bus able to accommodate multiple memory modules would vary its loading depending on the number of modules plugged in. Therefore, the circuit always provides the "perfect" impedance match for the system, eliminating potential noise and signal reflections.
To evaluate the performance of the termination scheme, a square wave was fed down a transmission line to a CMOS buffer containing the typical ESD protection diodes. The resulting ringing and noise was compared to a similar configuration that included the EZterm block inserted at the buffer's input. The diode-based results revealed a significant amount of overshoot and noise (Fig. 4a). A very clean signal was achieved with the EZterm circuit (Fig. 4b). The less noisy horizontal portions of the EZterm-clamped signal show the effect of leveraging the lower threshold voltage of the MOS devices—typically only tenths of a volt or so versus the 0.8- to 1.0-V for the diodes.
The EZterm circuit will be available in the form of a 16-channel standalone IC, the PAC NLT101. It will also be offered as a block of IP that can be licensed and then embedded in custom chip designs. The standalone chip provides dual-rail clamping—that is, clamping to both ground and power-supply rails—and bus termination independent of line impedance or loading conditions. In a typical application, four such chips could replace and outperform 64 conventional Schottky-diode pairs. The PAC NLT101 will be housed in a 24-lead QSOP surface-mount package, although the company is exploring the use of even smaller chip-scale packaging options.
The chip is targeted at 3.3-V (or lower) systems and has a maximum power dissipation of less than 0.9 W. In a 2.5-V system, the terminator will clamp voltage swings above VDD to 370 mV and below ground to 480 mV. In comparison, TTL diodes clamp the voltage swings above VDD to 840 mV, and below ground to 1200 mV.
As a block of IP, the EZterm circuit will be implemented in several forms. Designers will have available both a standard clamp termination block and a three-state-buffer implementation (Fig. 5). Initially, the company will offer the circuits using a generic 0.5-µm CMOS process. The processing needs, though, aren't very demanding, allowing other companies to rapidly port the IP to their own processes or to a foundry.
The company is considering additional circuit options as well. One could be a version including power-reducing circuitry that snoops the signal lines to look for bus activity. If no activity is detected, then the snoop circuitry will shut down the termination circuit to reduce power. An ideal use for such a block would be in circuits targeted at portable and other low-power applications.
Price & Availability
The PAC NLT101, when housed in a 24-lead plastic QSOP, will sell for about $1.00 each in lots of 100,000 units. Samples are immediately available. Several options are offered for the EZterm circuit when purchased as a block of IP. License fees for the IP can be arranged in a number of ways, depending on volume. But the most common agreement will include an up-front licensing fee and a small per-pin royalty. In addition, the company will offer a specially priced "early adopter" program as an incentive to initial licensees.
California Micro Devices Corp., 215 Topaz St., Milpitas, CA 95035-5430; Contact Peter McIntyre for business partnering and Jim Southerland for applications support at (408) 263-3214; www.calmicro.com.