SIC Of Figuring Out The Best ASIC Solution?

WHAT'S NEXT?
So now that you have an understanding of what's available in the ASIC market, how do you decide which solution is best for you? You should be able to narrow down your choices using the information in Table 1 and the flow comparison (Fig. 2).

One of the most powerful arguments for using an FPGA involves in-system programmability and reconfigurability, which has some ASIC vendors pondering whether to provide some form of reprogrammability. However, adding reconfigurability to an ASIC takes away some of its size, performance, and power benefits due to the overhead required for the reconfigurable fabric.

For instance, FPGAs like Xilinx's Virtex-5 utilize 65-nm process technology. This gives 90-nm-plus structured and platform ASICs less of a speed and power advantage over such FPGAs. By comparing design flows for FPGAs and ASICs, we can better understand the advantages and disadvantages to each type of approach (Fig. 2, again). The basic flows for each design implementation are quite similar, with some exceptions:

• The I/O design portion is greatly simplified for most ASIC implementations, since there's usually no need to design for I/O signal compatibility at the bank/region level. Designs that require several I/O standards must be compatible within a bank/region with respect to voltage, direction, and termination type. The requirement to have compatible I/O standards within a bank makes it more difficult to spread high-speed signals across banks to avoid issues with simultaneously switching output noise (SSO or SSN).
• Most FPGAs and some structured and platform ASICs don't require design for-test (DFT) implementations, such as scan path, built-in self test (BIST), and boundary-scan via JTAG. These DFT structures are usually built in.
• FPGAs and some structured/platform ASICs don't require design of the global and local clocking fabric. This provides a major time savings advantage in design, testing, and verification of the clock and logic fabric. The main disadvantage to a pre-defined clocking structure is the inherent inflexibility. Local/regional clocks only work with specific logic structures and their associated I/O pins. Figuring out which local/regional clocks work with which logic structures and I/O pins can be challenging and time consuming.
• FPGA design rule checks (DRCs): FPGAs don't need a physical DRC since all of the structures are predefined and pre-verified.
• Before any type of ASIC can be used, it must be sent to a fab. Typically, this requires advanced scheduling of several weeks or months. Also, the completed design implementation must arrive at the fab on time or you risk losing your spot in line. The fact that FPGAs are pre-fabricated gives them an advantage over ASICs, as the fabrication process can take several weeks for structured/ platform ASICs to several months for standard-cell ASICs. So if your entry into the market is timing-critical, consider prototyping with an FPGA and then make the move to some sort of ASIC if the number of units, speed, and other considerations warrant it.

GET READY TO RUMBLE
Looking ahead, it will be fun to watch the structured/platform ASIC vendors battle it out with the FPGA and standardcell ASIC vendors, which usually bodes well for the consumer in terms of pricing, technology, and selection. The structured/platform ASICs should steal more of both the FPGA and especially standard-cell ASIC market shares. In addition, companies like Open-Silicon are providing reduced-price custom ASICs that offer improved predictability and reliability.

Until recently, LSI Logic was a major player in the platform ASIC space with its RapidChip products. The company has since moved on to offering application-specific standard-product (ASSP) solutions. Will other companies follow suit? Also, it's likely that some of the smaller companies will get assimilated by larger ones. Stay tuned.