SPECIALTY MEMORY
Many industries impose special requirements on your system, such as military, aerospace, automotive, and medical. If your design has special
requirements, such as operating in extreme temperatures
or radiation hardening, consider companies that specialize
in memories for such environments. These include Austin Semiconductor, Aeroflex, Celis Semiconductor, Honeywell,
Maxwell Technologies, Pyramid Semiconductor, and QP
Semiconductor.
If you need a memory stackup solution, companies like
Irvine Sensors, which handles stacked ball-grid arrays
(BGAs), thin small-outline packages (TSOPs), bare dies, and
custom stacking, might offer an answer. You should also try
visiting helpful Web sites like Denali's ememory.com, which
includes a fully searchable database of datasheets, specifications, and simulation models for thousands of memory
components.
Another useful site, RAMpedia.com, is a DRAM memory
encyclopedia and reference tool to help hardware designers
with DRAM memory subsystems and address several memory-related challenges. "Designing a memory board means
a multitude of technical and industry issues must be
researched and their impact on the design interpreted,"
says Phan Hoang, director of research and development at
Virtium Technology.
"Thermal challenges, the need for extended functionalities, component availability, and end-of-life issues—
these demand considerable time and attention from
the engineer building a competitive design," adds
Hoang. "RAMpedia.com [provides] specs and simulation data in one convenient base of information" (see
"Table 3: Socket (Module) Versus Chip On-Board Tradeoffs,").
TO GO EMBEDDED OR OFF-CHIP
If you have the
"luxury" of using an application-specific standard product
(ASSP) or are designing an ASIC as part of your system
design, you're looking at some tough decisions. Foremost
among these is whether or not you're going to use embedded memory, and if so, how much should be included as
part of a system-on-a-chip (SoC) design (, again).
Guidelines are available for designers facing these choices (see "NVM Integration Ensures A Successful Experience,"). For example, if your SoC design requires more
advanced embedded-memory IP solutions to handle multiple memories and include integrated testing, consider companies like Aldec, ARM, Denali, Faraday Technology, Inapac
Technology, Sonics, and Virage Logic.
You could even opt for a system-in-package (SiP), package-in-package (PiP), or a stacked-die approach (see "Die
Stacking Solves The Mobile Device Memory Crunch,").
Companies selling multichip-package (MCP) memory and
die-stacking technology include Hynix, Micron, NEC, SacTec,
Samsung, Toshiba, and Vertical Circuits.
IBM's new PCB-like method of chip design, 3D chip stacking, stacks dies vertically and connects them using through-die vias. This considerably cuts down on wiring when compared to SiP, PiP, or MCP technologies. Using the new 3D
technology, a memory die (or dies) could sit directly on top of
a controller, which in turn could sit on top of a processor and
so on until you have an entire system stacked up vertically.
"[This new technology] allows [for] more interconnects
between chips. If chips sit next to each other [in] a package,
the wires that connect them together have to be very long
(at least as wide as the chip, maybe 1 to 2 cm)," says Steven J. Koester, manager of IBM's Exploratory CMOS Integration.
"Therefore, in order to keep the resistance low, the wires have to be ‘fat,' and so you cannot have too many wires connecting the chips to each other," he adds. "In 3D, since the
chips are stacked, they are very close together, so that the
wires between them are very short ([around] 1/1000 times
shorter). Therefore, the 3D interconnects can be very narrow, allowing me to have many more of them connecting the
chips. As long as we place the chip components that need
to ‘talk' to each other directly on top of each other, we can
eliminate the need for a lot of rerouting wiring on the chip."
So there you have it, your memory roadmap from now
until 2017 and... wait... what was my conclusion again?
REFERENCES
1. Nanotechnology Journal 18, "Electrostatically Telescoping Nanotube Nonvolatile Memory Device," IOP Publishing